256 lines
6.0 KiB
C
256 lines
6.0 KiB
C
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright 2009 Samsung Electronics Co.
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* Byungho Min <bhmin@samsung.com>
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*
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* Common Codes for S5PC100
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <clocksource/samsung_pwm.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/reboot.h>
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#include <asm/irq.h>
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#include <asm/proc-fns.h>
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#include <asm/system_misc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/map.h>
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#include <mach/hardware.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/sdhci.h>
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#include <plat/adc-core.h>
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#include <plat/ata-core.h>
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#include <plat/fb-core.h>
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#include <plat/iic-core.h>
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#include <plat/onenand-core.h>
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#include <plat/pwm-core.h>
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#include <plat/spi-core.h>
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#include <plat/watchdog-reset.h>
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#include "common.h"
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static const char name_s5pc100[] = "S5PC100";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = S5PC100_CPU_ID,
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.idmask = S5PC100_CPU_MASK,
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.map_io = s5pc100_map_io,
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.init_clocks = s5pc100_init_clocks,
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.init_uarts = s5pc100_init_uarts,
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.init = s5pc100_init,
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.name = name_s5pc100,
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},
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};
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/* Initial IO mappings */
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static struct map_desc s5pc100_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_CHIPID,
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.pfn = __phys_to_pfn(S5PC100_PA_CHIPID),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(S5PC100_PA_SYSCON),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(S5PC100_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_WATCHDOG,
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.pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(S5PC100_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SYSTIMER,
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.pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GPIO,
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.pfn = __phys_to_pfn(S5PC100_PA_GPIO),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC0,
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.pfn = __phys_to_pfn(S5PC100_PA_VIC0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC1,
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.pfn = __phys_to_pfn(S5PC100_PA_VIC1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)VA_VIC2,
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.pfn = __phys_to_pfn(S5PC100_PA_VIC2),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.length = SZ_512K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5PC100_VA_OTHERS,
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.pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}
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};
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static struct samsung_pwm_variant s5pc100_pwm_variant = {
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.bits = 32,
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.div_base = 0,
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.has_tint_cstat = true,
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.tclk_mask = (1 << 5),
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};
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void __init samsung_set_timer_source(unsigned int event, unsigned int source)
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{
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s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
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s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
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}
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void __init samsung_timer_init(void)
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{
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unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
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IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
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IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
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};
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samsung_pwm_clocksource_init(S3C_VA_TIMER,
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timer_irqs, &s5pc100_pwm_variant);
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}
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/*
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* s5pc100_map_io
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*
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* register the standard CPU IO areas
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*/
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void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
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{
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/* initialize the io descriptors we need for initialization */
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iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
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if (mach_desc)
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iotable_init(mach_desc, size);
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/* detect cpu id and rev. */
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s5p_init_cpu(S5P_VA_CHIPID);
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
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samsung_pwm_set_platdata(&s5pc100_pwm_variant);
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}
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void __init s5pc100_map_io(void)
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{
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/* initialise device information early */
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s5pc100_default_sdhci0();
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s5pc100_default_sdhci1();
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s5pc100_default_sdhci2();
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s3c_adc_setname("s3c64xx-adc");
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/* the i2c devices are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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s3c_i2c1_setname("s3c2440-i2c");
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s3c_onenand_setname("s5pc100-onenand");
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s3c_fb_setname("s5pc100-fb");
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s3c_cfcon_setname("s5pc100-pata");
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s3c64xx_spi_setname("s5pc100-spi");
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}
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void __init s5pc100_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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s3c24xx_register_baseclocks(xtal);
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s5p_register_clocks(xtal);
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s5pc100_register_clocks();
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s5pc100_setup_clocks();
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samsung_wdt_reset_init(S3C_VA_WATCHDOG);
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}
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void __init s5pc100_init_irq(void)
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{
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u32 vic[] = {~0, ~0, ~0};
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/* VIC0, VIC1, and VIC2 are fully populated. */
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s5p_init_irq(vic, ARRAY_SIZE(vic));
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}
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static struct bus_type s5pc100_subsys = {
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.name = "s5pc100-core",
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.dev_name = "s5pc100-core",
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};
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static struct device s5pc100_dev = {
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.bus = &s5pc100_subsys,
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};
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static int __init s5pc100_core_init(void)
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{
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return subsys_system_register(&s5pc100_subsys, NULL);
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}
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core_initcall(s5pc100_core_init);
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int __init s5pc100_init(void)
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{
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printk(KERN_INFO "S5PC100: Initializing architecture\n");
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return device_register(&s5pc100_dev);
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}
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/* uart registration process */
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void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
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}
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void s5pc100_restart(enum reboot_mode mode, const char *cmd)
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{
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if (mode != REBOOT_SOFT)
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samsung_wdt_reset();
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soft_restart(0);
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}
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