836 lines
20 KiB
C
836 lines
20 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi SoCs pinctrl driver
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*
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* Author: <alexandre.belloni@free-electrons.com>
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* License: Dual MIT/GPL
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "core.h"
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#include "pinconf.h"
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#include "pinmux.h"
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#define OCELOT_GPIO_OUT_SET 0x0
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#define OCELOT_GPIO_OUT_CLR 0x4
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#define OCELOT_GPIO_OUT 0x8
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#define OCELOT_GPIO_IN 0xc
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#define OCELOT_GPIO_OE 0x10
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#define OCELOT_GPIO_INTR 0x14
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#define OCELOT_GPIO_INTR_ENA 0x18
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#define OCELOT_GPIO_INTR_IDENT 0x1c
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#define OCELOT_GPIO_ALT0 0x20
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#define OCELOT_GPIO_ALT1 0x24
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#define OCELOT_GPIO_SD_MAP 0x28
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#define OCELOT_FUNC_PER_PIN 4
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enum {
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FUNC_NONE,
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FUNC_GPIO,
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FUNC_IRQ0_IN,
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FUNC_IRQ0_OUT,
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FUNC_IRQ1_IN,
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FUNC_IRQ1_OUT,
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FUNC_MIIM1,
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FUNC_MIIM2,
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FUNC_PCI_WAKE,
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FUNC_PTP0,
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FUNC_PTP1,
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FUNC_PTP2,
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FUNC_PTP3,
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FUNC_PWM,
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FUNC_RECO_CLK0,
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FUNC_RECO_CLK1,
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FUNC_SFP0,
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FUNC_SFP1,
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FUNC_SFP2,
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FUNC_SFP3,
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FUNC_SFP4,
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FUNC_SFP5,
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FUNC_SFP6,
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FUNC_SFP7,
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FUNC_SFP8,
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FUNC_SFP9,
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FUNC_SFP10,
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FUNC_SFP11,
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FUNC_SFP12,
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FUNC_SFP13,
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FUNC_SFP14,
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FUNC_SFP15,
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FUNC_SG0,
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FUNC_SG1,
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FUNC_SG2,
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FUNC_SI,
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FUNC_TACHO,
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FUNC_TWI,
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FUNC_TWI2,
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FUNC_TWI_SCL_M,
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FUNC_UART,
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FUNC_UART2,
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FUNC_MAX
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};
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static const char *const ocelot_function_names[] = {
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[FUNC_NONE] = "none",
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[FUNC_GPIO] = "gpio",
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[FUNC_IRQ0_IN] = "irq0_in",
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[FUNC_IRQ0_OUT] = "irq0_out",
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[FUNC_IRQ1_IN] = "irq1_in",
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[FUNC_IRQ1_OUT] = "irq1_out",
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[FUNC_MIIM1] = "miim1",
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[FUNC_MIIM2] = "miim2",
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[FUNC_PCI_WAKE] = "pci_wake",
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[FUNC_PTP0] = "ptp0",
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[FUNC_PTP1] = "ptp1",
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[FUNC_PTP2] = "ptp2",
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[FUNC_PTP3] = "ptp3",
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[FUNC_PWM] = "pwm",
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[FUNC_RECO_CLK0] = "reco_clk0",
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[FUNC_RECO_CLK1] = "reco_clk1",
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[FUNC_SFP0] = "sfp0",
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[FUNC_SFP1] = "sfp1",
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[FUNC_SFP2] = "sfp2",
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[FUNC_SFP3] = "sfp3",
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[FUNC_SFP4] = "sfp4",
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[FUNC_SFP5] = "sfp5",
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[FUNC_SFP6] = "sfp6",
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[FUNC_SFP7] = "sfp7",
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[FUNC_SFP8] = "sfp8",
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[FUNC_SFP9] = "sfp9",
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[FUNC_SFP10] = "sfp10",
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[FUNC_SFP11] = "sfp11",
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[FUNC_SFP12] = "sfp12",
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[FUNC_SFP13] = "sfp13",
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[FUNC_SFP14] = "sfp14",
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[FUNC_SFP15] = "sfp15",
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[FUNC_SG0] = "sg0",
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[FUNC_SG1] = "sg1",
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[FUNC_SG2] = "sg2",
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[FUNC_SI] = "si",
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[FUNC_TACHO] = "tacho",
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[FUNC_TWI] = "twi",
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[FUNC_TWI2] = "twi2",
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[FUNC_TWI_SCL_M] = "twi_scl_m",
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[FUNC_UART] = "uart",
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[FUNC_UART2] = "uart2",
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};
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struct ocelot_pmx_func {
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const char **groups;
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unsigned int ngroups;
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};
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struct ocelot_pin_caps {
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unsigned int pin;
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unsigned char functions[OCELOT_FUNC_PER_PIN];
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};
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struct ocelot_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctl;
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struct gpio_chip gpio_chip;
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struct regmap *map;
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struct pinctrl_desc *desc;
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struct ocelot_pmx_func func[FUNC_MAX];
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u8 stride;
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};
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#define OCELOT_P(p, f0, f1, f2) \
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static struct ocelot_pin_caps ocelot_pin_##p = { \
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.pin = p, \
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.functions = { \
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FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
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}, \
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}
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OCELOT_P(0, SG0, NONE, NONE);
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OCELOT_P(1, SG0, NONE, NONE);
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OCELOT_P(2, SG0, NONE, NONE);
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OCELOT_P(3, SG0, NONE, NONE);
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OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
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OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
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OCELOT_P(6, UART, TWI_SCL_M, NONE);
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OCELOT_P(7, UART, TWI_SCL_M, NONE);
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OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
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OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
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OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
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OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
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OCELOT_P(12, UART2, TWI_SCL_M, SFP2);
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OCELOT_P(13, UART2, TWI_SCL_M, SFP3);
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OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4);
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OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5);
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OCELOT_P(16, TWI, NONE, SI);
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OCELOT_P(17, TWI, TWI_SCL_M, SI);
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OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
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OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
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OCELOT_P(20, RECO_CLK0, TACHO, NONE);
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OCELOT_P(21, RECO_CLK1, PWM, NONE);
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#define OCELOT_PIN(n) { \
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.number = n, \
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.name = "GPIO_"#n, \
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.drv_data = &ocelot_pin_##n \
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}
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static const struct pinctrl_pin_desc ocelot_pins[] = {
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OCELOT_PIN(0),
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OCELOT_PIN(1),
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OCELOT_PIN(2),
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OCELOT_PIN(3),
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OCELOT_PIN(4),
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OCELOT_PIN(5),
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OCELOT_PIN(6),
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OCELOT_PIN(7),
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OCELOT_PIN(8),
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OCELOT_PIN(9),
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OCELOT_PIN(10),
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OCELOT_PIN(11),
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OCELOT_PIN(12),
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OCELOT_PIN(13),
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OCELOT_PIN(14),
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OCELOT_PIN(15),
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OCELOT_PIN(16),
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OCELOT_PIN(17),
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OCELOT_PIN(18),
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OCELOT_PIN(19),
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OCELOT_PIN(20),
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OCELOT_PIN(21),
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};
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#define JAGUAR2_P(p, f0, f1) \
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static struct ocelot_pin_caps jaguar2_pin_##p = { \
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.pin = p, \
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.functions = { \
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FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
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}, \
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}
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JAGUAR2_P(0, SG0, NONE);
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JAGUAR2_P(1, SG0, NONE);
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JAGUAR2_P(2, SG0, NONE);
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JAGUAR2_P(3, SG0, NONE);
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JAGUAR2_P(4, SG1, NONE);
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JAGUAR2_P(5, SG1, NONE);
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JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
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JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
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JAGUAR2_P(8, PTP0, NONE);
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JAGUAR2_P(9, PTP1, NONE);
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JAGUAR2_P(10, UART, NONE);
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JAGUAR2_P(11, UART, NONE);
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JAGUAR2_P(12, SG1, NONE);
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JAGUAR2_P(13, SG1, NONE);
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JAGUAR2_P(14, TWI, TWI_SCL_M);
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JAGUAR2_P(15, TWI, NONE);
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JAGUAR2_P(16, SI, TWI_SCL_M);
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JAGUAR2_P(17, SI, TWI_SCL_M);
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JAGUAR2_P(18, SI, TWI_SCL_M);
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JAGUAR2_P(19, PCI_WAKE, NONE);
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JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
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JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
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JAGUAR2_P(22, TACHO, NONE);
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JAGUAR2_P(23, PWM, NONE);
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JAGUAR2_P(24, UART2, NONE);
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JAGUAR2_P(25, UART2, SI);
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JAGUAR2_P(26, PTP2, SI);
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JAGUAR2_P(27, PTP3, SI);
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JAGUAR2_P(28, TWI2, SI);
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JAGUAR2_P(29, TWI2, SI);
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JAGUAR2_P(30, SG2, SI);
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JAGUAR2_P(31, SG2, SI);
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JAGUAR2_P(32, SG2, SI);
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JAGUAR2_P(33, SG2, SI);
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JAGUAR2_P(34, NONE, TWI_SCL_M);
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JAGUAR2_P(35, NONE, TWI_SCL_M);
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JAGUAR2_P(36, NONE, TWI_SCL_M);
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JAGUAR2_P(37, NONE, TWI_SCL_M);
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JAGUAR2_P(38, NONE, TWI_SCL_M);
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JAGUAR2_P(39, NONE, TWI_SCL_M);
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JAGUAR2_P(40, NONE, TWI_SCL_M);
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JAGUAR2_P(41, NONE, TWI_SCL_M);
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JAGUAR2_P(42, NONE, TWI_SCL_M);
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JAGUAR2_P(43, NONE, TWI_SCL_M);
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JAGUAR2_P(44, NONE, SFP8);
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JAGUAR2_P(45, NONE, SFP9);
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JAGUAR2_P(46, NONE, SFP10);
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JAGUAR2_P(47, NONE, SFP11);
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JAGUAR2_P(48, SFP0, NONE);
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JAGUAR2_P(49, SFP1, SI);
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JAGUAR2_P(50, SFP2, SI);
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JAGUAR2_P(51, SFP3, SI);
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JAGUAR2_P(52, SFP4, NONE);
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JAGUAR2_P(53, SFP5, NONE);
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JAGUAR2_P(54, SFP6, NONE);
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JAGUAR2_P(55, SFP7, NONE);
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JAGUAR2_P(56, MIIM1, SFP12);
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JAGUAR2_P(57, MIIM1, SFP13);
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JAGUAR2_P(58, MIIM2, SFP14);
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JAGUAR2_P(59, MIIM2, SFP15);
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JAGUAR2_P(60, NONE, NONE);
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JAGUAR2_P(61, NONE, NONE);
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JAGUAR2_P(62, NONE, NONE);
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JAGUAR2_P(63, NONE, NONE);
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#define JAGUAR2_PIN(n) { \
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.number = n, \
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.name = "GPIO_"#n, \
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.drv_data = &jaguar2_pin_##n \
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}
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static const struct pinctrl_pin_desc jaguar2_pins[] = {
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JAGUAR2_PIN(0),
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JAGUAR2_PIN(1),
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JAGUAR2_PIN(2),
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JAGUAR2_PIN(3),
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JAGUAR2_PIN(4),
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JAGUAR2_PIN(5),
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JAGUAR2_PIN(6),
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JAGUAR2_PIN(7),
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JAGUAR2_PIN(8),
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JAGUAR2_PIN(9),
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JAGUAR2_PIN(10),
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JAGUAR2_PIN(11),
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JAGUAR2_PIN(12),
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JAGUAR2_PIN(13),
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JAGUAR2_PIN(14),
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JAGUAR2_PIN(15),
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JAGUAR2_PIN(16),
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JAGUAR2_PIN(17),
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JAGUAR2_PIN(18),
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JAGUAR2_PIN(19),
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JAGUAR2_PIN(20),
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JAGUAR2_PIN(21),
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JAGUAR2_PIN(22),
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JAGUAR2_PIN(23),
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JAGUAR2_PIN(24),
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JAGUAR2_PIN(25),
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JAGUAR2_PIN(26),
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JAGUAR2_PIN(27),
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JAGUAR2_PIN(28),
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JAGUAR2_PIN(29),
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JAGUAR2_PIN(30),
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JAGUAR2_PIN(31),
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JAGUAR2_PIN(32),
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JAGUAR2_PIN(33),
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JAGUAR2_PIN(34),
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JAGUAR2_PIN(35),
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JAGUAR2_PIN(36),
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JAGUAR2_PIN(37),
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JAGUAR2_PIN(38),
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JAGUAR2_PIN(39),
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JAGUAR2_PIN(40),
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JAGUAR2_PIN(41),
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JAGUAR2_PIN(42),
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JAGUAR2_PIN(43),
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JAGUAR2_PIN(44),
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JAGUAR2_PIN(45),
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JAGUAR2_PIN(46),
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JAGUAR2_PIN(47),
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JAGUAR2_PIN(48),
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JAGUAR2_PIN(49),
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JAGUAR2_PIN(50),
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JAGUAR2_PIN(51),
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JAGUAR2_PIN(52),
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JAGUAR2_PIN(53),
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JAGUAR2_PIN(54),
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JAGUAR2_PIN(55),
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JAGUAR2_PIN(56),
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JAGUAR2_PIN(57),
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JAGUAR2_PIN(58),
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JAGUAR2_PIN(59),
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JAGUAR2_PIN(60),
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JAGUAR2_PIN(61),
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JAGUAR2_PIN(62),
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JAGUAR2_PIN(63),
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};
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static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
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{
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return ARRAY_SIZE(ocelot_function_names);
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}
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static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
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unsigned int function)
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{
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return ocelot_function_names[function];
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}
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static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
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unsigned int function,
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const char *const **groups,
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unsigned *const num_groups)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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*groups = info->func[function].groups;
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*num_groups = info->func[function].ngroups;
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return 0;
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}
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static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
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unsigned int pin, unsigned int function)
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{
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struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
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int i;
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for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
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if (function == p->functions[i])
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return i;
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}
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return -1;
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}
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#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
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static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
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unsigned int selector, unsigned int group)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
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unsigned int p = pin->pin % 32;
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int f;
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f = ocelot_pin_function_idx(info, group, selector);
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if (f < 0)
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return -EINVAL;
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/*
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* f is encoded on two bits.
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* bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
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* ALT[1]
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* This is racy because both registers can't be updated at the same time
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* but it doesn't matter much for now.
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*/
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regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
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BIT(p), f << p);
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regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
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BIT(p), f << (p - 1));
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return 0;
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}
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#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
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static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int pin, bool input)
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{
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struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
|
unsigned int p = pin % 32;
|
|
|
|
regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
|
|
input ? 0 : BIT(p));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned int offset)
|
|
{
|
|
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
|
unsigned int p = offset % 32;
|
|
|
|
regmap_update_bits(info->map, REG_ALT(0, info, offset),
|
|
BIT(p), 0);
|
|
regmap_update_bits(info->map, REG_ALT(1, info, offset),
|
|
BIT(p), 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pinmux_ops ocelot_pmx_ops = {
|
|
.get_functions_count = ocelot_get_functions_count,
|
|
.get_function_name = ocelot_get_function_name,
|
|
.get_function_groups = ocelot_get_function_groups,
|
|
.set_mux = ocelot_pinmux_set_mux,
|
|
.gpio_set_direction = ocelot_gpio_set_direction,
|
|
.gpio_request_enable = ocelot_gpio_request_enable,
|
|
};
|
|
|
|
static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
|
|
{
|
|
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return info->desc->npins;
|
|
}
|
|
|
|
static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
|
|
unsigned int group)
|
|
{
|
|
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return info->desc->pins[group].name;
|
|
}
|
|
|
|
static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
|
|
unsigned int group,
|
|
const unsigned int **pins,
|
|
unsigned int *num_pins)
|
|
{
|
|
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
*pins = &info->desc->pins[group].number;
|
|
*num_pins = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pinctrl_ops ocelot_pctl_ops = {
|
|
.get_groups_count = ocelot_pctl_get_groups_count,
|
|
.get_group_name = ocelot_pctl_get_group_name,
|
|
.get_group_pins = ocelot_pctl_get_group_pins,
|
|
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
|
|
.dt_free_map = pinconf_generic_dt_free_map,
|
|
};
|
|
|
|
static struct pinctrl_desc ocelot_desc = {
|
|
.name = "ocelot-pinctrl",
|
|
.pins = ocelot_pins,
|
|
.npins = ARRAY_SIZE(ocelot_pins),
|
|
.pctlops = &ocelot_pctl_ops,
|
|
.pmxops = &ocelot_pmx_ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static struct pinctrl_desc jaguar2_desc = {
|
|
.name = "jaguar2-pinctrl",
|
|
.pins = jaguar2_pins,
|
|
.npins = ARRAY_SIZE(jaguar2_pins),
|
|
.pctlops = &ocelot_pctl_ops,
|
|
.pmxops = &ocelot_pmx_ops,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static int ocelot_create_group_func_map(struct device *dev,
|
|
struct ocelot_pinctrl *info)
|
|
{
|
|
int f, npins, i;
|
|
u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
|
|
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
|
|
for (f = 0; f < FUNC_MAX; f++) {
|
|
for (npins = 0, i = 0; i < info->desc->npins; i++) {
|
|
if (ocelot_pin_function_idx(info, i, f) >= 0)
|
|
pins[npins++] = i;
|
|
}
|
|
|
|
if (!npins)
|
|
continue;
|
|
|
|
info->func[f].ngroups = npins;
|
|
info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
|
|
GFP_KERNEL);
|
|
if (!info->func[f].groups) {
|
|
kfree(pins);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
for (i = 0; i < npins; i++)
|
|
info->func[f].groups[i] = info->desc->pins[pins[i]].name;
|
|
}
|
|
|
|
kfree(pins);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ocelot_pinctrl_register(struct platform_device *pdev,
|
|
struct ocelot_pinctrl *info)
|
|
{
|
|
int ret;
|
|
|
|
ret = ocelot_create_group_func_map(&pdev->dev, info);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Unable to create group func map.\n");
|
|
return ret;
|
|
}
|
|
|
|
info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
|
|
if (IS_ERR(info->pctl)) {
|
|
dev_err(&pdev->dev, "Failed to register pinctrl\n");
|
|
return PTR_ERR(info->pctl);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
|
{
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
unsigned int val;
|
|
|
|
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
|
|
|
|
return !!(val & BIT(offset % 32));
|
|
}
|
|
|
|
static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
|
int value)
|
|
{
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
|
|
if (value)
|
|
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
|
|
BIT(offset % 32));
|
|
else
|
|
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
|
|
BIT(offset % 32));
|
|
}
|
|
|
|
static int ocelot_gpio_get_direction(struct gpio_chip *chip,
|
|
unsigned int offset)
|
|
{
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
unsigned int val;
|
|
|
|
regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
|
|
|
|
return !(val & BIT(offset % 32));
|
|
}
|
|
|
|
static int ocelot_gpio_direction_input(struct gpio_chip *chip,
|
|
unsigned int offset)
|
|
{
|
|
return pinctrl_gpio_direction_input(chip->base + offset);
|
|
}
|
|
|
|
static int ocelot_gpio_direction_output(struct gpio_chip *chip,
|
|
unsigned int offset, int value)
|
|
{
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
unsigned int pin = BIT(offset % 32);
|
|
|
|
if (value)
|
|
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
|
|
pin);
|
|
else
|
|
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
|
|
pin);
|
|
|
|
return pinctrl_gpio_direction_output(chip->base + offset);
|
|
}
|
|
|
|
static const struct gpio_chip ocelot_gpiolib_chip = {
|
|
.request = gpiochip_generic_request,
|
|
.free = gpiochip_generic_free,
|
|
.set = ocelot_gpio_set,
|
|
.get = ocelot_gpio_get,
|
|
.get_direction = ocelot_gpio_get_direction,
|
|
.direction_input = ocelot_gpio_direction_input,
|
|
.direction_output = ocelot_gpio_direction_output,
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
static void ocelot_irq_mask(struct irq_data *data)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
unsigned int gpio = irqd_to_hwirq(data);
|
|
|
|
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
|
|
BIT(gpio % 32), 0);
|
|
}
|
|
|
|
static void ocelot_irq_unmask(struct irq_data *data)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
unsigned int gpio = irqd_to_hwirq(data);
|
|
|
|
regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
|
|
BIT(gpio % 32), BIT(gpio % 32));
|
|
}
|
|
|
|
static void ocelot_irq_ack(struct irq_data *data)
|
|
{
|
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
unsigned int gpio = irqd_to_hwirq(data);
|
|
|
|
regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
|
|
BIT(gpio % 32), BIT(gpio % 32));
|
|
}
|
|
|
|
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
|
|
|
|
static struct irq_chip ocelot_eoi_irqchip = {
|
|
.name = "gpio",
|
|
.irq_mask = ocelot_irq_mask,
|
|
.irq_eoi = ocelot_irq_ack,
|
|
.irq_unmask = ocelot_irq_unmask,
|
|
.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
|
|
.irq_set_type = ocelot_irq_set_type,
|
|
};
|
|
|
|
static struct irq_chip ocelot_irqchip = {
|
|
.name = "gpio",
|
|
.irq_mask = ocelot_irq_mask,
|
|
.irq_ack = ocelot_irq_ack,
|
|
.irq_unmask = ocelot_irq_unmask,
|
|
.irq_set_type = ocelot_irq_set_type,
|
|
};
|
|
|
|
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
|
|
{
|
|
type &= IRQ_TYPE_SENSE_MASK;
|
|
|
|
if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
|
|
return -EINVAL;
|
|
|
|
if (type & IRQ_TYPE_LEVEL_HIGH)
|
|
irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
|
|
handle_fasteoi_irq, NULL);
|
|
if (type & IRQ_TYPE_EDGE_BOTH)
|
|
irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
|
|
handle_edge_irq, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ocelot_irq_handler(struct irq_desc *desc)
|
|
{
|
|
struct irq_chip *parent_chip = irq_desc_get_chip(desc);
|
|
struct gpio_chip *chip = irq_desc_get_handler_data(desc);
|
|
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
|
unsigned int reg = 0, irq, i;
|
|
unsigned long irqs;
|
|
|
|
for (i = 0; i < info->stride; i++) {
|
|
regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®);
|
|
if (!reg)
|
|
continue;
|
|
|
|
chained_irq_enter(parent_chip, desc);
|
|
|
|
irqs = reg;
|
|
|
|
for_each_set_bit(irq, &irqs,
|
|
min(32U, info->desc->npins - 32 * i))
|
|
generic_handle_irq(irq_linear_revmap(chip->irq.domain,
|
|
irq + 32 * i));
|
|
|
|
chained_irq_exit(parent_chip, desc);
|
|
}
|
|
}
|
|
|
|
static int ocelot_gpiochip_register(struct platform_device *pdev,
|
|
struct ocelot_pinctrl *info)
|
|
{
|
|
struct gpio_chip *gc;
|
|
struct gpio_irq_chip *girq;
|
|
int ret, irq;
|
|
|
|
info->gpio_chip = ocelot_gpiolib_chip;
|
|
|
|
gc = &info->gpio_chip;
|
|
gc->ngpio = info->desc->npins;
|
|
gc->parent = &pdev->dev;
|
|
gc->base = 0;
|
|
gc->of_node = info->dev->of_node;
|
|
gc->label = "ocelot-gpio";
|
|
|
|
irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
|
|
if (irq <= 0)
|
|
return irq;
|
|
|
|
girq = &gc->irq;
|
|
girq->chip = &ocelot_irqchip;
|
|
girq->parent_handler = ocelot_irq_handler;
|
|
girq->num_parents = 1;
|
|
girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
|
|
GFP_KERNEL);
|
|
if (!girq->parents)
|
|
return -ENOMEM;
|
|
girq->parents[0] = irq;
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_edge_irq;
|
|
|
|
ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id ocelot_pinctrl_of_match[] = {
|
|
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
|
|
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
|
|
{},
|
|
};
|
|
|
|
static int ocelot_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct ocelot_pinctrl *info;
|
|
void __iomem *base;
|
|
int ret;
|
|
struct regmap_config regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
};
|
|
|
|
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
|
|
if (!info)
|
|
return -ENOMEM;
|
|
|
|
info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
|
|
|
|
base = devm_ioremap_resource(dev,
|
|
platform_get_resource(pdev, IORESOURCE_MEM, 0));
|
|
if (IS_ERR(base)) {
|
|
dev_err(dev, "Failed to ioremap registers\n");
|
|
return PTR_ERR(base);
|
|
}
|
|
|
|
info->stride = 1 + (info->desc->npins - 1) / 32;
|
|
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
|
|
|
|
info->map = devm_regmap_init_mmio(dev, base, ®map_config);
|
|
if (IS_ERR(info->map)) {
|
|
dev_err(dev, "Failed to create regmap\n");
|
|
return PTR_ERR(info->map);
|
|
}
|
|
dev_set_drvdata(dev, info->map);
|
|
info->dev = dev;
|
|
|
|
ret = ocelot_pinctrl_register(pdev, info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ocelot_gpiochip_register(pdev, info);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ocelot_pinctrl_driver = {
|
|
.driver = {
|
|
.name = "pinctrl-ocelot",
|
|
.of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = ocelot_pinctrl_probe,
|
|
};
|
|
builtin_platform_driver(ocelot_pinctrl_driver);
|