146 lines
4.6 KiB
C
146 lines
4.6 KiB
C
/*****************************************************************************
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* *
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* File: cpl5_cmd.h *
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* $Revision: 1.6 $ *
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* $Date: 2005/06/21 18:29:47 $ *
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* Description: *
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* part of the Chelsio 10Gb Ethernet Driver. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License, version 2, as *
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* published by the Free Software Foundation. *
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* *
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* You should have received a copy of the GNU General Public License along *
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* with this program; if not, write to the Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
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* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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* *
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* http://www.chelsio.com *
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* *
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* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
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* All rights reserved. *
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* *
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* Maintainers: maintainers@chelsio.com *
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* *
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* Authors: Dimitrios Michailidis <dm@chelsio.com> *
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* Tina Yang <tainay@chelsio.com> *
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* Felix Marti <felix@chelsio.com> *
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* Scott Bardone <sbardone@chelsio.com> *
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* Kurt Ottaway <kottaway@chelsio.com> *
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* Frank DiMambro <frank@chelsio.com> *
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* *
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* History: *
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* *
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****************************************************************************/
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#ifndef _CXGB_CPL5_CMD_H_
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#define _CXGB_CPL5_CMD_H_
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#include <asm/byteorder.h>
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#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
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#error "Adjust your <asm/byteorder.h> defines"
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#endif
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enum CPL_opcode {
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CPL_RX_PKT = 0xAD,
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CPL_TX_PKT = 0xB2,
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CPL_TX_PKT_LSO = 0xB6,
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};
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enum { /* TX_PKT_LSO ethernet types */
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CPL_ETH_II,
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CPL_ETH_II_VLAN,
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CPL_ETH_802_3,
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CPL_ETH_802_3_VLAN
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};
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struct cpl_rx_data {
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u32 rsvd0;
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u32 len;
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u32 seq;
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u16 urg;
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u8 rsvd1;
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u8 status;
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};
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/*
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* We want this header's alignment to be no more stringent than 2-byte aligned.
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* All fields are u8 or u16 except for the length. However that field is not
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* used so we break it into 2 16-bit parts to easily meet our alignment needs.
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*/
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struct cpl_tx_pkt {
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u8 opcode;
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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u8 iff:4;
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u8 ip_csum_dis:1;
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u8 l4_csum_dis:1;
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u8 vlan_valid:1;
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u8 rsvd:1;
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#else
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u8 rsvd:1;
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u8 vlan_valid:1;
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u8 l4_csum_dis:1;
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u8 ip_csum_dis:1;
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u8 iff:4;
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#endif
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u16 vlan;
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u16 len_hi;
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u16 len_lo;
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};
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struct cpl_tx_pkt_lso {
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u8 opcode;
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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u8 iff:4;
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u8 ip_csum_dis:1;
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u8 l4_csum_dis:1;
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u8 vlan_valid:1;
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u8 rsvd:1;
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#else
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u8 rsvd:1;
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u8 vlan_valid:1;
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u8 l4_csum_dis:1;
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u8 ip_csum_dis:1;
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u8 iff:4;
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#endif
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u16 vlan;
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u32 len;
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u32 rsvd2;
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u8 rsvd3;
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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u8 tcp_hdr_words:4;
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u8 ip_hdr_words:4;
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#else
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u8 ip_hdr_words:4;
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u8 tcp_hdr_words:4;
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#endif
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u16 eth_type_mss;
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};
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struct cpl_rx_pkt {
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u8 opcode;
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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u8 iff:4;
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u8 csum_valid:1;
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u8 bad_pkt:1;
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u8 vlan_valid:1;
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u8 rsvd:1;
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#else
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u8 rsvd:1;
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u8 vlan_valid:1;
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u8 bad_pkt:1;
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u8 csum_valid:1;
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u8 iff:4;
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#endif
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u16 csum;
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u16 vlan;
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u16 len;
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};
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#endif /* _CXGB_CPL5_CMD_H_ */
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