197 lines
4.0 KiB
Plaintext
197 lines
4.0 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "marvell,kirkwood";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,feroceon";
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clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
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clock-names = "cpu_clk", "ddrclk", "powersave";
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};
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};
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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};
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intc: interrupt-controller {
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compatible = "marvell,orion-intc", "marvell,intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xf1020204 0x04>,
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<0xf1020214 0x04>;
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};
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ocp@f1000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0xf1000000 0x0100000
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0xe0000000 0xe0000000 0x8100000 /* PCIE */
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0xf4000000 0xf4000000 0x0000400
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0xf5000000 0xf5000000 0x0000400>;
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#address-cells = <1>;
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#size-cells = <1>;
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core_clk: core-clocks@10030 {
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compatible = "marvell,kirkwood-core-clock";
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reg = <0x10030 0x4>;
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#clock-cells = <1>;
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};
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gpio0: gpio@10100 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0x10100 0x40>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <35>, <36>, <37>, <38>;
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clocks = <&gate_clk 7>;
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};
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gpio1: gpio@10140 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0x10140 0x40>;
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ngpios = <18>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <39>, <40>, <41>;
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clocks = <&gate_clk 7>;
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};
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serial@12000 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <33>;
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clocks = <&gate_clk 7>;
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status = "disabled";
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};
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serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <34>;
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clocks = <&gate_clk 7>;
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status = "disabled";
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};
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spi@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <23>;
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reg = <0x10600 0x28>;
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clocks = <&gate_clk 7>;
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status = "disabled";
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};
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gate_clk: clock-gating-control@2011c {
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compatible = "marvell,kirkwood-gating-clock";
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reg = <0x2011c 0x4>;
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clocks = <&core_clk 0>;
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#clock-cells = <1>;
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};
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wdt@20300 {
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compatible = "marvell,orion-wdt";
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reg = <0x20300 0x28>;
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clocks = <&gate_clk 7>;
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status = "okay";
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};
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xor@60800 {
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compatible = "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60A00 0x100>;
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status = "okay";
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clocks = <&gate_clk 8>;
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xor00 {
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interrupts = <5>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <6>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0xd0B00 0x100>;
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status = "okay";
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clocks = <&gate_clk 16>;
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xor00 {
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interrupts = <7>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <8>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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ehci@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <19>;
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clocks = <&gate_clk 3>;
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status = "okay";
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};
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nand@3000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cle = <0>;
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ale = <1>;
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bank-width = <1>;
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compatible = "marvell,orion-nand";
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reg = <0xf4000000 0x400>;
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chip-delay = <25>;
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/* set partition map and/or chip-delay in board dts */
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clocks = <&gate_clk 7>;
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status = "disabled";
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};
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i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <29>;
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clock-frequency = <100000>;
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clocks = <&gate_clk 7>;
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status = "disabled";
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};
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crypto@30000 {
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compatible = "marvell,orion-crypto";
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reg = <0x30000 0x10000>,
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<0xf5000000 0x800>;
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reg-names = "regs", "sram";
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interrupts = <22>;
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clocks = <&gate_clk 17>;
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status = "okay";
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};
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};
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};
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