611 lines
15 KiB
C
611 lines
15 KiB
C
/*
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* GPMC support functions
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*
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* Copyright (C) 2005-2006 Nokia Corporation
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*
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* Author: Juha Yrjola
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/ioport.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <asm/mach-types.h>
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#include <plat/gpmc.h>
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#include <plat/sdrc.h>
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/* GPMC register offsets */
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#define GPMC_REVISION 0x00
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#define GPMC_SYSCONFIG 0x10
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#define GPMC_SYSSTATUS 0x14
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#define GPMC_IRQSTATUS 0x18
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#define GPMC_IRQENABLE 0x1c
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#define GPMC_TIMEOUT_CONTROL 0x40
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#define GPMC_ERR_ADDRESS 0x44
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#define GPMC_ERR_TYPE 0x48
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#define GPMC_CONFIG 0x50
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#define GPMC_STATUS 0x54
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#define GPMC_PREFETCH_CONFIG1 0x1e0
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#define GPMC_PREFETCH_CONFIG2 0x1e4
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#define GPMC_PREFETCH_CONTROL 0x1ec
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#define GPMC_PREFETCH_STATUS 0x1f0
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#define GPMC_ECC_CONFIG 0x1f4
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#define GPMC_ECC_CONTROL 0x1f8
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#define GPMC_ECC_SIZE_CONFIG 0x1fc
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#define GPMC_CS0 0x60
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#define GPMC_CS_SIZE 0x30
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#define GPMC_MEM_START 0x00000000
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#define GPMC_MEM_END 0x3FFFFFFF
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#define BOOT_ROM_SPACE 0x100000 /* 1MB */
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#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
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#define GPMC_SECTION_SHIFT 28 /* 128 MB */
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#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
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#define CS_NUM_SHIFT 24
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#define ENABLE_PREFETCH (0x1 << 7)
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#define DMA_MPU_MODE 2
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/* Structure to save gpmc cs context */
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struct gpmc_cs_config {
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u32 config1;
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u32 config2;
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u32 config3;
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u32 config4;
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u32 config5;
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u32 config6;
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u32 config7;
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int is_valid;
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};
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/*
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* Structure to save/restore gpmc context
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* to support core off on OMAP3
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*/
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struct omap3_gpmc_regs {
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u32 sysconfig;
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u32 irqenable;
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u32 timeout_ctrl;
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u32 config;
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u32 prefetch_config1;
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u32 prefetch_config2;
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u32 prefetch_control;
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struct gpmc_cs_config cs_context[GPMC_CS_NUM];
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};
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static struct resource gpmc_mem_root;
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static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
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static unsigned gpmc_cs_map;
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static void __iomem *gpmc_base;
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static struct clk *gpmc_l3_clk;
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static void gpmc_write_reg(int idx, u32 val)
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{
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__raw_writel(val, gpmc_base + idx);
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}
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static u32 gpmc_read_reg(int idx)
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{
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return __raw_readl(gpmc_base + idx);
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}
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void gpmc_cs_write_reg(int cs, int idx, u32 val)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
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__raw_writel(val, reg_addr);
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}
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u32 gpmc_cs_read_reg(int cs, int idx)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
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return __raw_readl(reg_addr);
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}
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/* TODO: Add support for gpmc_fck to clock framework and use it */
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unsigned long gpmc_get_fclk_period(void)
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{
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unsigned long rate = clk_get_rate(gpmc_l3_clk);
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if (rate == 0) {
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printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
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return 0;
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}
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rate /= 1000;
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rate = 1000000000 / rate; /* In picoseconds */
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return rate;
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}
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unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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{
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unsigned long tick_ps;
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/* Calculate in picosecs to yield more exact results */
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tick_ps = gpmc_get_fclk_period();
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return (time_ns * 1000 + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_ticks_to_ns(unsigned int ticks)
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{
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return ticks * gpmc_get_fclk_period() / 1000;
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}
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unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
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{
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unsigned long ticks = gpmc_ns_to_ticks(time_ns);
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return ticks * gpmc_get_fclk_period() / 1000;
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}
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#ifdef DEBUG
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static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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int time, const char *name)
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#else
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static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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int time)
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#endif
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{
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u32 l;
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int ticks, mask, nr_bits;
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if (time == 0)
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ticks = 0;
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else
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ticks = gpmc_ns_to_ticks(time);
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nr_bits = end_bit - st_bit + 1;
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if (ticks >= 1 << nr_bits) {
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#ifdef DEBUG
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printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
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cs, name, time, ticks, 1 << nr_bits);
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#endif
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return -1;
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}
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mask = (1 << nr_bits) - 1;
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l = gpmc_cs_read_reg(cs, reg);
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#ifdef DEBUG
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printk(KERN_INFO
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"GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
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cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
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(l >> st_bit) & mask, time);
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#endif
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l &= ~(mask << st_bit);
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l |= ticks << st_bit;
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gpmc_cs_write_reg(cs, reg, l);
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return 0;
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}
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#ifdef DEBUG
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#define GPMC_SET_ONE(reg, st, end, field) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
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t->field, #field) < 0) \
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return -1
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#else
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#define GPMC_SET_ONE(reg, st, end, field) \
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if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
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return -1
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#endif
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int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
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{
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int div;
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u32 l;
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l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
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div = l / gpmc_get_fclk_period();
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if (div > 4)
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return -1;
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if (div <= 0)
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div = 1;
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return div;
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}
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int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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{
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int div;
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u32 l;
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div = gpmc_cs_calc_divider(cs, t->sync_clk);
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if (div < 0)
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return -1;
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
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GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
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GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
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if (cpu_is_omap34xx()) {
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
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}
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/* caller is expected to have initialized CONFIG1 to cover
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* at least sync vs async
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*/
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
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#ifdef DEBUG
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printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
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cs, (div * gpmc_get_fclk_period()) / 1000, div);
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#endif
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l &= ~0x03;
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l |= (div - 1);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
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}
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return 0;
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}
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static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
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{
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u32 l;
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u32 mask;
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mask = (1 << GPMC_SECTION_SHIFT) - size;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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l &= ~0x3f;
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l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
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l &= ~(0x0f << 8);
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l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
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l |= GPMC_CONFIG7_CSVALID;
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
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}
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static void gpmc_cs_disable_mem(int cs)
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{
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u32 l;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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l &= ~GPMC_CONFIG7_CSVALID;
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
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}
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static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
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{
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u32 l;
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u32 mask;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
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mask = (l >> 8) & 0x0f;
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*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
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}
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static int gpmc_cs_mem_enabled(int cs)
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{
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u32 l;
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
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return l & GPMC_CONFIG7_CSVALID;
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}
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int gpmc_cs_set_reserved(int cs, int reserved)
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{
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if (cs > GPMC_CS_NUM)
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return -ENODEV;
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gpmc_cs_map &= ~(1 << cs);
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gpmc_cs_map |= (reserved ? 1 : 0) << cs;
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return 0;
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}
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int gpmc_cs_reserved(int cs)
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{
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if (cs > GPMC_CS_NUM)
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return -ENODEV;
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return gpmc_cs_map & (1 << cs);
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}
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static unsigned long gpmc_mem_align(unsigned long size)
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{
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int order;
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size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
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order = GPMC_CHUNK_SHIFT - 1;
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do {
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size >>= 1;
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order++;
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} while (size);
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size = 1 << order;
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return size;
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}
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static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
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{
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struct resource *res = &gpmc_cs_mem[cs];
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int r;
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size = gpmc_mem_align(size);
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spin_lock(&gpmc_mem_lock);
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res->start = base;
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res->end = base + size - 1;
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r = request_resource(&gpmc_mem_root, res);
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spin_unlock(&gpmc_mem_lock);
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return r;
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}
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int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
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{
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struct resource *res = &gpmc_cs_mem[cs];
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int r = -1;
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if (cs > GPMC_CS_NUM)
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return -ENODEV;
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size = gpmc_mem_align(size);
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if (size > (1 << GPMC_SECTION_SHIFT))
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return -ENOMEM;
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spin_lock(&gpmc_mem_lock);
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if (gpmc_cs_reserved(cs)) {
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r = -EBUSY;
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goto out;
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}
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if (gpmc_cs_mem_enabled(cs))
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r = adjust_resource(res, res->start & ~(size - 1), size);
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if (r < 0)
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r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
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size, NULL, NULL);
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if (r < 0)
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goto out;
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gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
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*base = res->start;
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gpmc_cs_set_reserved(cs, 1);
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out:
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spin_unlock(&gpmc_mem_lock);
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return r;
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}
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EXPORT_SYMBOL(gpmc_cs_request);
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void gpmc_cs_free(int cs)
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{
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spin_lock(&gpmc_mem_lock);
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if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
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printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
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BUG();
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spin_unlock(&gpmc_mem_lock);
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return;
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}
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gpmc_cs_disable_mem(cs);
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release_resource(&gpmc_cs_mem[cs]);
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gpmc_cs_set_reserved(cs, 0);
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spin_unlock(&gpmc_mem_lock);
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}
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EXPORT_SYMBOL(gpmc_cs_free);
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/**
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* gpmc_prefetch_enable - configures and starts prefetch transfer
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* @cs: nand cs (chip select) number
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* @dma_mode: dma mode enable (1) or disable (0)
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* @u32_count: number of bytes to be transferred
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* @is_write: prefetch read(0) or write post(1) mode
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*/
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int gpmc_prefetch_enable(int cs, int dma_mode,
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unsigned int u32_count, int is_write)
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{
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uint32_t prefetch_config1;
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if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
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/* Set the amount of bytes to be prefetched */
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gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
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/* Set dma/mpu mode, the prefetch read / post write and
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* enable the engine. Set which cs is has requested for.
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*/
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prefetch_config1 = ((cs << CS_NUM_SHIFT) |
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PREFETCH_FIFOTHRESHOLD |
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ENABLE_PREFETCH |
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(dma_mode << DMA_MPU_MODE) |
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(0x1 & is_write));
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gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
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} else {
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return -EBUSY;
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}
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/* Start the prefetch engine */
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gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
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return 0;
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}
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EXPORT_SYMBOL(gpmc_prefetch_enable);
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/**
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* gpmc_prefetch_reset - disables and stops the prefetch engine
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*/
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void gpmc_prefetch_reset(void)
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{
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/* Stop the PFPW engine */
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gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
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/* Reset/disable the PFPW engine */
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gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
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}
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EXPORT_SYMBOL(gpmc_prefetch_reset);
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/**
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* gpmc_prefetch_status - reads prefetch status of engine
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*/
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int gpmc_prefetch_status(void)
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{
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return gpmc_read_reg(GPMC_PREFETCH_STATUS);
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}
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EXPORT_SYMBOL(gpmc_prefetch_status);
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static void __init gpmc_mem_init(void)
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{
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int cs;
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unsigned long boot_rom_space = 0;
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/* never allocate the first page, to facilitate bug detection;
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* even if we didn't boot from ROM.
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*/
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boot_rom_space = BOOT_ROM_SPACE;
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/* In apollon the CS0 is mapped as 0x0000 0000 */
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if (machine_is_omap_apollon())
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boot_rom_space = 0;
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gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
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gpmc_mem_root.end = GPMC_MEM_END;
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/* Reserve all regions that has been set up by bootloader */
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for (cs = 0; cs < GPMC_CS_NUM; cs++) {
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u32 base, size;
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if (!gpmc_cs_mem_enabled(cs))
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continue;
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gpmc_cs_get_memconf(cs, &base, &size);
|
|
if (gpmc_cs_insert_mem(cs, base, size) < 0)
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
void __init gpmc_init(void)
|
|
{
|
|
u32 l;
|
|
char *ck;
|
|
|
|
if (cpu_is_omap24xx()) {
|
|
ck = "core_l3_ck";
|
|
if (cpu_is_omap2420())
|
|
l = OMAP2420_GPMC_BASE;
|
|
else
|
|
l = OMAP34XX_GPMC_BASE;
|
|
} else if (cpu_is_omap34xx()) {
|
|
ck = "gpmc_fck";
|
|
l = OMAP34XX_GPMC_BASE;
|
|
} else if (cpu_is_omap44xx()) {
|
|
ck = "gpmc_fck";
|
|
l = OMAP44XX_GPMC_BASE;
|
|
}
|
|
|
|
gpmc_l3_clk = clk_get(NULL, ck);
|
|
if (IS_ERR(gpmc_l3_clk)) {
|
|
printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
|
|
BUG();
|
|
}
|
|
|
|
gpmc_base = ioremap(l, SZ_4K);
|
|
if (!gpmc_base) {
|
|
clk_put(gpmc_l3_clk);
|
|
printk(KERN_ERR "Could not get GPMC register memory\n");
|
|
BUG();
|
|
}
|
|
|
|
l = gpmc_read_reg(GPMC_REVISION);
|
|
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
|
|
/* Set smart idle mode and automatic L3 clock gating */
|
|
l = gpmc_read_reg(GPMC_SYSCONFIG);
|
|
l &= 0x03 << 3;
|
|
l |= (0x02 << 3) | (1 << 0);
|
|
gpmc_write_reg(GPMC_SYSCONFIG, l);
|
|
gpmc_mem_init();
|
|
}
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct omap3_gpmc_regs gpmc_context;
|
|
|
|
void omap3_gpmc_save_context()
|
|
{
|
|
int i;
|
|
gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
|
|
gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
|
|
gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
|
|
gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
|
|
gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
|
|
gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
|
|
gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
|
|
for (i = 0; i < GPMC_CS_NUM; i++) {
|
|
gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
|
|
if (gpmc_context.cs_context[i].is_valid) {
|
|
gpmc_context.cs_context[i].config1 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
|
|
gpmc_context.cs_context[i].config2 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
|
|
gpmc_context.cs_context[i].config3 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
|
|
gpmc_context.cs_context[i].config4 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
|
|
gpmc_context.cs_context[i].config5 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
|
|
gpmc_context.cs_context[i].config6 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
|
|
gpmc_context.cs_context[i].config7 =
|
|
gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
|
|
}
|
|
}
|
|
}
|
|
|
|
void omap3_gpmc_restore_context()
|
|
{
|
|
int i;
|
|
gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
|
|
gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
|
|
gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
|
|
gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
|
|
gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
|
|
gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
|
|
gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
|
|
for (i = 0; i < GPMC_CS_NUM; i++) {
|
|
if (gpmc_context.cs_context[i].is_valid) {
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
|
|
gpmc_context.cs_context[i].config1);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
|
|
gpmc_context.cs_context[i].config2);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
|
|
gpmc_context.cs_context[i].config3);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
|
|
gpmc_context.cs_context[i].config4);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
|
|
gpmc_context.cs_context[i].config5);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
|
|
gpmc_context.cs_context[i].config6);
|
|
gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
|
|
gpmc_context.cs_context[i].config7);
|
|
}
|
|
}
|
|
}
|
|
#endif /* CONFIG_ARCH_OMAP3 */
|