560 lines
18 KiB
C
560 lines
18 KiB
C
/*
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* OMAP2/3 CM module functions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <plat/hardware.h>
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#include "iomap.h"
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#include "common.h"
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#include "cm.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
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#define DPLL_AUTOIDLE_DISABLE 0x0
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#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3
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/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
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#define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0
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#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
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static const u8 cm_idlest_offs[] = {
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CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
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};
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u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
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{
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return __raw_readl(cm_base + module + idx);
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}
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void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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__raw_writel(val, cm_base + module + idx);
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}
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/* Read-modify-write a register in a CM module. Caller must lock */
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u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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omap2_cm_write_mod_reg(v, module, idx);
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return v;
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}
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u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
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}
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u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
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}
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/*
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*
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*/
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static void _write_clktrctrl(u8 c, s16 module, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
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v &= ~mask;
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v |= c << __ffs(mask);
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omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
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}
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bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
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{
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u32 v;
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bool ret = 0;
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BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
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v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
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v &= mask;
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v >>= __ffs(mask);
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if (cpu_is_omap24xx())
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ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
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else
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ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
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return ret;
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}
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void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
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}
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void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
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}
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void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
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}
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void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
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}
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void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
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}
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void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
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{
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_write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
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}
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/*
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* DPLL autoidle control
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*/
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static void _omap2xxx_set_dpll_autoidle(u8 m)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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v &= ~OMAP24XX_AUTO_DPLL_MASK;
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v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
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omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
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}
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void omap2xxx_cm_set_dpll_disable_autoidle(void)
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{
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_omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
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}
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void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
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{
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_omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
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}
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/*
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* APLL autoidle control
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*/
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static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
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{
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u32 v;
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v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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v &= ~mask;
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v |= m << __ffs(mask);
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omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
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}
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void omap2xxx_cm_set_apll54_disable_autoidle(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
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OMAP24XX_AUTO_54M_MASK);
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}
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void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
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OMAP24XX_AUTO_54M_MASK);
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}
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void omap2xxx_cm_set_apll96_disable_autoidle(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
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OMAP24XX_AUTO_96M_MASK);
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}
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void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
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{
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_omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
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OMAP24XX_AUTO_96M_MASK);
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}
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/*
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*
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*/
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/**
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* omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
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* @prcm_mod: PRCM module offset
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* @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
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* @idlest_shift: shift of the bit in the CM_IDLEST* register to check
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*
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* XXX document
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*/
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int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
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{
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int ena = 0, i = 0;
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u8 cm_idlest_reg;
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u32 mask;
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if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
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return -EINVAL;
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cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
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mask = 1 << idlest_shift;
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if (cpu_is_omap24xx())
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ena = mask;
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else if (cpu_is_omap34xx())
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ena = 0;
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else
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BUG();
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omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
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MAX_MODULE_READY_TIME, i);
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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/*
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* Context save/restore code - OMAP3 only
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*/
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#ifdef CONFIG_ARCH_OMAP3
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struct omap3_cm_regs {
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u32 iva2_cm_clksel1;
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u32 iva2_cm_clksel2;
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u32 cm_sysconfig;
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u32 sgx_cm_clksel;
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u32 dss_cm_clksel;
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u32 cam_cm_clksel;
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u32 per_cm_clksel;
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u32 emu_cm_clksel;
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u32 emu_cm_clkstctrl;
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u32 pll_cm_autoidle;
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u32 pll_cm_autoidle2;
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u32 pll_cm_clksel4;
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u32 pll_cm_clksel5;
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u32 pll_cm_clken2;
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u32 cm_polctrl;
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u32 iva2_cm_fclken;
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u32 iva2_cm_clken_pll;
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u32 core_cm_fclken1;
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u32 core_cm_fclken3;
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u32 sgx_cm_fclken;
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u32 wkup_cm_fclken;
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u32 dss_cm_fclken;
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u32 cam_cm_fclken;
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u32 per_cm_fclken;
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u32 usbhost_cm_fclken;
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u32 core_cm_iclken1;
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u32 core_cm_iclken2;
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u32 core_cm_iclken3;
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u32 sgx_cm_iclken;
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u32 wkup_cm_iclken;
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u32 dss_cm_iclken;
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u32 cam_cm_iclken;
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u32 per_cm_iclken;
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u32 usbhost_cm_iclken;
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u32 iva2_cm_autoidle2;
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u32 mpu_cm_autoidle2;
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u32 iva2_cm_clkstctrl;
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u32 mpu_cm_clkstctrl;
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u32 core_cm_clkstctrl;
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u32 sgx_cm_clkstctrl;
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u32 dss_cm_clkstctrl;
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u32 cam_cm_clkstctrl;
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u32 per_cm_clkstctrl;
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u32 neon_cm_clkstctrl;
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u32 usbhost_cm_clkstctrl;
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u32 core_cm_autoidle1;
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u32 core_cm_autoidle2;
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u32 core_cm_autoidle3;
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u32 wkup_cm_autoidle;
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u32 dss_cm_autoidle;
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u32 cam_cm_autoidle;
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u32 per_cm_autoidle;
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u32 usbhost_cm_autoidle;
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u32 sgx_cm_sleepdep;
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u32 dss_cm_sleepdep;
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u32 cam_cm_sleepdep;
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u32 per_cm_sleepdep;
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u32 usbhost_cm_sleepdep;
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u32 cm_clkout_ctrl;
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};
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static struct omap3_cm_regs cm_context;
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void omap3_cm_save_context(void)
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{
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cm_context.iva2_cm_clksel1 =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
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cm_context.iva2_cm_clksel2 =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
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cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
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cm_context.sgx_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
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cm_context.dss_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
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cm_context.cam_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
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cm_context.per_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
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cm_context.emu_cm_clksel =
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omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
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cm_context.emu_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
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/*
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* As per erratum i671, ROM code does not respect the PER DPLL
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* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
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* In this case, even though this register has been saved in
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* scratchpad contents, we need to restore AUTO_PERIPH_DPLL
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* by ourselves. So, we need to save it anyway.
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*/
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cm_context.pll_cm_autoidle =
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omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
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cm_context.pll_cm_autoidle2 =
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omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
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cm_context.pll_cm_clksel4 =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
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cm_context.pll_cm_clksel5 =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
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cm_context.pll_cm_clken2 =
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omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
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cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
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cm_context.iva2_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
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cm_context.iva2_cm_clken_pll =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
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cm_context.core_cm_fclken1 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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cm_context.core_cm_fclken3 =
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omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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cm_context.sgx_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
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cm_context.wkup_cm_fclken =
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omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
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cm_context.dss_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
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cm_context.cam_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
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cm_context.per_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
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cm_context.usbhost_cm_fclken =
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omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
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cm_context.core_cm_iclken1 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
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cm_context.core_cm_iclken2 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
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cm_context.core_cm_iclken3 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
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cm_context.sgx_cm_iclken =
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omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
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cm_context.wkup_cm_iclken =
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omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
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cm_context.dss_cm_iclken =
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omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
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cm_context.cam_cm_iclken =
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omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
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cm_context.per_cm_iclken =
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omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
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cm_context.usbhost_cm_iclken =
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omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
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cm_context.iva2_cm_autoidle2 =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
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cm_context.mpu_cm_autoidle2 =
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omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
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cm_context.iva2_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.mpu_cm_clkstctrl =
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omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.core_cm_clkstctrl =
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omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.sgx_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.dss_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.cam_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.per_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.neon_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
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cm_context.usbhost_cm_clkstctrl =
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omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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OMAP2_CM_CLKSTCTRL);
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cm_context.core_cm_autoidle1 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
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cm_context.core_cm_autoidle2 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
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cm_context.core_cm_autoidle3 =
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omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
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cm_context.wkup_cm_autoidle =
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omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
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cm_context.dss_cm_autoidle =
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omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
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cm_context.cam_cm_autoidle =
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omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
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|
cm_context.per_cm_autoidle =
|
|
omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
|
|
cm_context.usbhost_cm_autoidle =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
|
|
cm_context.sgx_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_context.dss_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
|
|
cm_context.cam_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
|
|
cm_context.per_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
|
|
cm_context.usbhost_cm_sleepdep =
|
|
omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_context.cm_clkout_ctrl =
|
|
omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
|
|
OMAP3_CM_CLKOUT_CTRL_OFFSET);
|
|
}
|
|
|
|
void omap3_cm_restore_context(void)
|
|
{
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
|
|
CM_CLKSEL1);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
|
|
CM_CLKSEL2);
|
|
__raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
|
|
CM_CLKSEL);
|
|
omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
|
|
CM_CLKSEL1);
|
|
omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
/*
|
|
* As per erratum i671, ROM code does not respect the PER DPLL
|
|
* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
|
|
* In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
|
|
*/
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKSEL4);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKSEL5);
|
|
omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKEN2);
|
|
__raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
|
|
OMAP3430_CM_CLKEN_PLL);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
|
|
CM_FCLKEN1);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
|
|
OMAP3430ES2_CM_FCLKEN3);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
|
|
CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
|
|
OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
|
|
CM_ICLKEN1);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
|
|
CM_ICLKEN2);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
|
|
CM_ICLKEN3);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
|
|
CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
|
|
OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
|
|
OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
|
|
CM_AUTOIDLE1);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
|
|
CM_AUTOIDLE2);
|
|
omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
|
|
CM_AUTOIDLE3);
|
|
omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
|
|
CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
|
|
OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
|
|
omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
|
|
OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
|
|
omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
|
|
OMAP3_CM_CLKOUT_CTRL_OFFSET);
|
|
}
|
|
#endif
|