230 lines
6.1 KiB
C
230 lines
6.1 KiB
C
/*
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* OMAP4 CPU idle Routines
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/export.h>
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#include <linux/clockchips.h>
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#include <asm/proc-fns.h>
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#include "common.h"
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#include "pm.h"
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#include "prm.h"
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#ifdef CONFIG_CPU_IDLE
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/* Machine specific information to be recorded in the C-state driver_data */
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struct omap4_idle_statedata {
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u32 cpu_state;
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u32 mpu_logic_state;
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u32 mpu_state;
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u8 valid;
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};
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static struct cpuidle_params cpuidle_params_table[] = {
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/* C1 - CPU0 ON + CPU1 ON + MPU ON */
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{.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
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/* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
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{.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
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/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
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{.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
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};
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#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
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struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
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static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
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/**
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* omap4_enter_idle - Programs OMAP4 to enter the specified state
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* @dev: cpuidle device
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* @drv: cpuidle driver
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* @index: the index of state to be entered
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*
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* Called from the CPUidle framework to program the device to the
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* specified low power state selected by the governor.
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* Returns the amount of time spent in the low power state.
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*/
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static int omap4_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv,
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int index)
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{
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struct omap4_idle_statedata *cx =
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cpuidle_get_statedata(&dev->states_usage[index]);
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u32 cpu1_state;
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int cpu_id = smp_processor_id();
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local_fiq_disable();
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/*
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* CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
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* This is necessary to honour hardware recommondation
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* of triggeing all the possible low power modes once CPU1 is
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* out of coherency and in OFF mode.
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* Update dev->last_state so that governor stats reflects right
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* data.
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*/
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cpu1_state = pwrdm_read_pwrst(cpu1_pd);
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if (cpu1_state != PWRDM_POWER_OFF) {
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index = drv->safe_state_index;
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cx = cpuidle_get_statedata(&dev->states_usage[index]);
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}
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if (index > 0)
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
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/*
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* Call idle CPU PM enter notifier chain so that
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* VFP and per CPU interrupt context is saved.
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*/
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if (cx->cpu_state == PWRDM_POWER_OFF)
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cpu_pm_enter();
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pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
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omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
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/*
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* Call idle CPU cluster PM enter notifier chain
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* to save GIC and wakeupgen context.
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*/
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if ((cx->mpu_state == PWRDM_POWER_RET) &&
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(cx->mpu_logic_state == PWRDM_POWER_OFF))
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cpu_cluster_pm_enter();
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omap4_enter_lowpower(dev->cpu, cx->cpu_state);
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/*
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* Call idle CPU PM exit notifier chain to restore
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* VFP and per CPU IRQ context. Only CPU0 state is
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* considered since CPU1 is managed by CPU hotplug.
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*/
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if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
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cpu_pm_exit();
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/*
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* Call idle CPU cluster PM exit notifier chain
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* to restore GIC and wakeupgen context.
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*/
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if (omap4_mpuss_read_prev_context_state())
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cpu_cluster_pm_exit();
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if (index > 0)
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
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local_fiq_enable();
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return index;
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}
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DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
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struct cpuidle_driver omap4_idle_driver = {
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.name = "omap4_idle",
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.owner = THIS_MODULE,
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.en_core_tk_irqen = 1,
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};
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static inline void _fill_cstate(struct cpuidle_driver *drv,
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int idx, const char *descr)
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{
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struct cpuidle_state *state = &drv->states[idx];
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state->exit_latency = cpuidle_params_table[idx].exit_latency;
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state->target_residency = cpuidle_params_table[idx].target_residency;
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state->flags = CPUIDLE_FLAG_TIME_VALID;
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state->enter = omap4_enter_idle;
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sprintf(state->name, "C%d", idx + 1);
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strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
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}
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static inline struct omap4_idle_statedata *_fill_cstate_usage(
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struct cpuidle_device *dev,
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int idx)
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{
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struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
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struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
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cx->valid = cpuidle_params_table[idx].valid;
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cpuidle_set_statedata(state_usage, cx);
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return cx;
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}
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/**
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* omap4_idle_init - Init routine for OMAP4 idle
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*
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* Registers the OMAP4 specific cpuidle driver to the cpuidle
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* framework with the valid set of states.
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*/
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int __init omap4_idle_init(void)
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{
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struct omap4_idle_statedata *cx;
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struct cpuidle_device *dev;
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struct cpuidle_driver *drv = &omap4_idle_driver;
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unsigned int cpu_id = 0;
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mpu_pd = pwrdm_lookup("mpu_pwrdm");
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cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
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cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
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if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
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return -ENODEV;
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drv->safe_state_index = -1;
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dev = &per_cpu(omap4_idle_dev, cpu_id);
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dev->cpu = cpu_id;
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/* C1 - CPU0 ON + CPU1 ON + MPU ON */
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_fill_cstate(drv, 0, "MPUSS ON");
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drv->safe_state_index = 0;
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cx = _fill_cstate_usage(dev, 0);
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cx->valid = 1; /* C1 is always valid */
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cx->cpu_state = PWRDM_POWER_ON;
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cx->mpu_state = PWRDM_POWER_ON;
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cx->mpu_logic_state = PWRDM_POWER_RET;
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/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
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_fill_cstate(drv, 1, "MPUSS CSWR");
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cx = _fill_cstate_usage(dev, 1);
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cx->cpu_state = PWRDM_POWER_OFF;
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cx->mpu_state = PWRDM_POWER_RET;
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cx->mpu_logic_state = PWRDM_POWER_RET;
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/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
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_fill_cstate(drv, 2, "MPUSS OSWR");
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cx = _fill_cstate_usage(dev, 2);
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cx->cpu_state = PWRDM_POWER_OFF;
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cx->mpu_state = PWRDM_POWER_RET;
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cx->mpu_logic_state = PWRDM_POWER_OFF;
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drv->state_count = OMAP4_NUM_STATES;
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cpuidle_register_driver(&omap4_idle_driver);
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dev->state_count = OMAP4_NUM_STATES;
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if (cpuidle_register_device(dev)) {
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pr_err("%s: CPUidle register device failed\n", __func__);
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return -EIO;
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}
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return 0;
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}
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#else
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int __init omap4_idle_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_CPU_IDLE */
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