311 lines
9.0 KiB
C
311 lines
9.0 KiB
C
/*
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* OMAP2/3 PRM module functions
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*
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* Copyright (C) 2010-2011 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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* Benoît Cousson
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "common.h"
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#include <plat/cpu.h>
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#include <plat/prcm.h>
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#include <plat/irqs.h>
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#include "vp.h"
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#include "prm2xxx_3xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "prm-regbits-24xx.h"
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#include "prm-regbits-34xx.h"
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static const struct omap_prcm_irq omap3_prcm_irqs[] = {
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OMAP_PRCM_IRQ("wkup", 0, 0),
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OMAP_PRCM_IRQ("io", 9, 1),
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};
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static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
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.ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
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.mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
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.nr_regs = 1,
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.irqs = omap3_prcm_irqs,
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.nr_irqs = ARRAY_SIZE(omap3_prcm_irqs),
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.irq = INT_34XX_PRCM_MPU_IRQ,
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.read_pending_irqs = &omap3xxx_prm_read_pending_irqs,
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.ocp_barrier = &omap3xxx_prm_ocp_barrier,
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.save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
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.restore_irqen = &omap3xxx_prm_restore_irqen,
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};
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u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
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{
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return __raw_readl(prm_base + module + idx);
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}
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void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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__raw_writel(val, prm_base + module + idx);
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}
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/* Read-modify-write a register in a PRM module. Caller must lock */
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u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
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{
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u32 v;
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v = omap2_prm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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omap2_prm_write_mod_reg(v, module, idx);
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return v;
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}
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/* Read a PRM register, AND it, and shift the result down to bit 0 */
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u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
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{
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u32 v;
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v = omap2_prm_read_mod_reg(domain, idx);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
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}
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u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
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}
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/**
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* omap2_prm_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* @prm_mod: PRM submodule base (e.g. CORE_MOD)
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* @shift: register bit shift corresponding to the reset line to check
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*
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* Returns 1 if the (sub)module hardreset line is currently asserted,
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* 0 if the (sub)module hardreset line is not currently asserted, or
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* -EINVAL if called while running on a non-OMAP2/3 chip.
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*/
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int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
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{
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if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
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return -EINVAL;
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return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
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(1 << shift));
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}
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/**
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* omap2_prm_assert_hardreset - assert the HW reset line of a submodule
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* @prm_mod: PRM submodule base (e.g. CORE_MOD)
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* @shift: register bit shift corresponding to the reset line to assert
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*
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* Some IPs like dsp or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* place the submodule into reset. Returns 0 upon success or -EINVAL
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* upon an argument error.
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*/
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int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
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{
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u32 mask;
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if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
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return -EINVAL;
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mask = 1 << shift;
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omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
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return 0;
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}
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/**
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* omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait
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* @prm_mod: PRM submodule base (e.g. CORE_MOD)
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* @rst_shift: register bit shift corresponding to the reset line to deassert
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* @st_shift: register bit shift for the status of the deasserted submodule
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*
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* Some IPs like dsp or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* take the submodule out of reset and wait until the PRCM indicates
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* that the reset has completed before returning. Returns 0 upon success or
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* -EINVAL upon an argument error, -EEXIST if the submodule was already out
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
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{
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u32 rst, st;
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int c;
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if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
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return -EINVAL;
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rst = 1 << rst_shift;
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st = 1 << st_shift;
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/* Check the current status to avoid de-asserting the line twice */
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if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
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/* de-assert the reset control line */
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omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
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/* wait the status to be set */
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omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
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st),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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}
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/* PRM VP */
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/*
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* struct omap3_vp - OMAP3 VP register access description.
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* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
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*/
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struct omap3_vp {
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u32 tranxdone_status;
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};
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static struct omap3_vp omap3_vp[] = {
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[OMAP3_VP_VDD_MPU_ID] = {
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.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
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},
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[OMAP3_VP_VDD_CORE_ID] = {
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.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
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},
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};
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#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
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u32 omap3_prm_vp_check_txdone(u8 vp_id)
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{
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struct omap3_vp *vp = &omap3_vp[vp_id];
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u32 irqstatus;
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irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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return irqstatus & vp->tranxdone_status;
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}
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void omap3_prm_vp_clear_txdone(u8 vp_id)
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{
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struct omap3_vp *vp = &omap3_vp[vp_id];
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omap2_prm_write_mod_reg(vp->tranxdone_status,
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OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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}
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u32 omap3_prm_vcvp_read(u8 offset)
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{
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return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
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}
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void omap3_prm_vcvp_write(u32 val, u8 offset)
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{
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omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
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}
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u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
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{
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return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
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}
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/**
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* omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
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* @events: ptr to a u32, preallocated by caller
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*
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* Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
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* MPU IRQs, and store the result into the u32 pointed to by @events.
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* No return value.
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*/
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void omap3xxx_prm_read_pending_irqs(unsigned long *events)
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{
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u32 mask, st;
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/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
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mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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events[0] = mask & st;
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}
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/**
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* omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
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*
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* Force any buffered writes to the PRM IP block to complete. Needed
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* by the PRM IRQ handler, which reads and writes directly to the IP
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* block, to avoid race conditions after acknowledging or clearing IRQ
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* bits. No return value.
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*/
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void omap3xxx_prm_ocp_barrier(void)
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{
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omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
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}
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/**
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* omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
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* @saved_mask: ptr to a u32 array to save IRQENABLE bits
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*
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* Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
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* must be allocated by the caller. Intended to be used in the PRM
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* interrupt handler suspend callback. The OCP barrier is needed to
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* ensure the write to disable PRM interrupts reaches the PRM before
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* returning; otherwise, spurious interrupts might occur. No return
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* value.
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*/
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void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
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{
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saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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/* OCP barrier */
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omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
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}
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/**
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* omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
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* @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
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*
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* Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
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* to be used in the PRM interrupt handler resume callback to restore
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* values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
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* barrier should be needed here; any pending PRM interrupts will fire
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* once the writes reach the PRM. No return value.
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*/
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void omap3xxx_prm_restore_irqen(u32 *saved_mask)
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{
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omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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}
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static int __init omap3xxx_prcm_init(void)
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{
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if (cpu_is_omap34xx())
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return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
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return 0;
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}
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subsys_initcall(omap3xxx_prcm_init);
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