888 lines
22 KiB
C
888 lines
22 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/console.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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static const char radeon_family_name[][16] = {
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"R100",
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"RV100",
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"RS100",
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"RV200",
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"RS200",
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"R200",
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"RV250",
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"RS300",
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"RV280",
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"R300",
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"R350",
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"RV350",
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"RV380",
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"R420",
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"R423",
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"RV410",
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"RS400",
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"RS480",
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"RS600",
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"RS690",
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"RS740",
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"RV515",
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"R520",
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"RV530",
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"RV560",
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"RV570",
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"R580",
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"R600",
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"RV610",
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"RV630",
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"RV670",
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"RV620",
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"RV635",
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"RS780",
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"RS880",
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"RV770",
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"RV730",
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"RV710",
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"RV740",
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"CEDAR",
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"REDWOOD",
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"JUNIPER",
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"CYPRESS",
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"HEMLOCK",
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"LAST",
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};
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/*
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* Clear GPU surface registers.
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*/
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void radeon_surface_init(struct radeon_device *rdev)
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{
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/* FIXME: check this out */
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if (rdev->family < CHIP_R600) {
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int i;
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for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
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if (rdev->surface_regs[i].bo)
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radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
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else
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radeon_clear_surface_reg(rdev, i);
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}
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/* enable surfaces */
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WREG32(RADEON_SURFACE_CNTL, 0);
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}
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}
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/*
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* GPU scratch registers helpers function.
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*/
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void radeon_scratch_init(struct radeon_device *rdev)
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{
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int i;
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/* FIXME: check this out */
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if (rdev->family < CHIP_R300) {
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rdev->scratch.num_reg = 5;
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} else {
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rdev->scratch.num_reg = 7;
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}
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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rdev->scratch.free[i] = true;
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rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
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}
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}
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.free[i]) {
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rdev->scratch.free[i] = false;
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*reg = rdev->scratch.reg[i];
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return 0;
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}
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}
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return -EINVAL;
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}
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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if (rdev->scratch.reg[i] == reg) {
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rdev->scratch.free[i] = true;
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return;
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}
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}
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}
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/**
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* radeon_vram_location - try to find VRAM location
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* @rdev: radeon device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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* @base: base address at which to put VRAM
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*
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* Function will place try to place VRAM at base address provided
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* as parameter (which is so far either PCI aperture address or
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* for IGP TOM base address).
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*
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* If there is not enough space to fit the unvisible VRAM in the 32bits
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* address space then we limit the VRAM size to the aperture.
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*
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* If we are using AGP and if the AGP aperture doesn't allow us to have
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* room for all the VRAM than we restrict the VRAM to the PCI aperture
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* size and print a warning.
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*
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* This function will never fails, worst case are limiting VRAM.
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*
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* Note: GTT start, end, size should be initialized before calling this
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* function on AGP platform.
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*
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* Note: We don't explictly enforce VRAM start to be aligned on VRAM size,
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* this shouldn't be a problem as we are using the PCI aperture as a reference.
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* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
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* not IGP.
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*
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* Note: we use mc_vram_size as on some board we need to program the mc to
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* cover the whole aperture even if VRAM size is inferior to aperture size
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* Novell bug 204882 + along with lots of ubuntu ones
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*
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* Note: when limiting vram it's safe to overwritte real_vram_size because
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* we are not in case where real_vram_size is inferior to mc_vram_size (ie
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* note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
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* ones)
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*
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* Note: IGP TOM addr should be the same as the aperture addr, we don't
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* explicitly check for that thought.
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*
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* FIXME: when reducing VRAM size align new size on power of 2.
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*/
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void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
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{
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mc->vram_start = base;
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if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
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dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
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mc->real_vram_size = mc->aper_size;
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mc->mc_vram_size = mc->aper_size;
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}
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_end <= mc->gtt_end) {
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dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
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mc->real_vram_size = mc->aper_size;
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mc->mc_vram_size = mc->aper_size;
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}
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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}
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/**
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* radeon_gtt_location - try to find GTT location
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* @rdev: radeon device structure holding all necessary informations
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* @mc: memory controller structure holding memory informations
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*
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* Function will place try to place GTT before or after VRAM.
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*
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* If GTT size is bigger than space left then we ajust GTT size.
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* Thus function will never fails.
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*
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* FIXME: when reducing GTT size align new size on power of 2.
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*/
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void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
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{
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u64 size_af, size_bf;
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size_af = 0xFFFFFFFF - mc->vram_end;
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size_bf = mc->vram_start;
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if (size_bf > size_af) {
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if (mc->gtt_size > size_bf) {
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dev_warn(rdev->dev, "limiting GTT\n");
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mc->gtt_size = size_bf;
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}
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mc->gtt_start = mc->vram_start - mc->gtt_size;
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} else {
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if (mc->gtt_size > size_af) {
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dev_warn(rdev->dev, "limiting GTT\n");
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mc->gtt_size = size_af;
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}
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mc->gtt_start = mc->vram_end + 1;
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}
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mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
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dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
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mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
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}
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/*
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* GPU helpers function.
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*/
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bool radeon_card_posted(struct radeon_device *rdev)
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{
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uint32_t reg;
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/* first check CRTCs */
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if (ASIC_IS_DCE4(rdev)) {
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reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
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RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
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if (reg & EVERGREEN_CRTC_MASTER_EN)
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return true;
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} else if (ASIC_IS_AVIVO(rdev)) {
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reg = RREG32(AVIVO_D1CRTC_CONTROL) |
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RREG32(AVIVO_D2CRTC_CONTROL);
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if (reg & AVIVO_CRTC_EN) {
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return true;
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}
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} else {
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reg = RREG32(RADEON_CRTC_GEN_CNTL) |
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RREG32(RADEON_CRTC2_GEN_CNTL);
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if (reg & RADEON_CRTC_EN) {
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return true;
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}
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}
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/* then check MEM_SIZE, in case the crtcs are off */
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if (rdev->family >= CHIP_R600)
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reg = RREG32(R600_CONFIG_MEMSIZE);
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else
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reg = RREG32(RADEON_CONFIG_MEMSIZE);
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if (reg)
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return true;
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return false;
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}
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void radeon_update_bandwidth_info(struct radeon_device *rdev)
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{
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fixed20_12 a;
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u32 sclk, mclk;
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if (rdev->flags & RADEON_IS_IGP) {
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sclk = radeon_get_engine_clock(rdev);
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mclk = rdev->clock.default_mclk;
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a.full = dfixed_const(100);
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rdev->pm.sclk.full = dfixed_const(sclk);
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rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
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rdev->pm.mclk.full = dfixed_const(mclk);
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rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
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a.full = dfixed_const(16);
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/* core_bandwidth = sclk(Mhz) * 16 */
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rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
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} else {
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sclk = radeon_get_engine_clock(rdev);
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mclk = radeon_get_memory_clock(rdev);
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a.full = dfixed_const(100);
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rdev->pm.sclk.full = dfixed_const(sclk);
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rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
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rdev->pm.mclk.full = dfixed_const(mclk);
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rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
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}
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}
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bool radeon_boot_test_post_card(struct radeon_device *rdev)
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{
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if (radeon_card_posted(rdev))
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return true;
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if (rdev->bios) {
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DRM_INFO("GPU not posted. posting now...\n");
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if (rdev->is_atom_bios)
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atom_asic_init(rdev->mode_info.atom_context);
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else
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radeon_combios_asic_init(rdev->ddev);
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return true;
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} else {
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dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
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return false;
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}
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}
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int radeon_dummy_page_init(struct radeon_device *rdev)
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{
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if (rdev->dummy_page.page)
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return 0;
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rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
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if (rdev->dummy_page.page == NULL)
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return -ENOMEM;
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rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
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0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (!rdev->dummy_page.addr) {
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__free_page(rdev->dummy_page.page);
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rdev->dummy_page.page = NULL;
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return -ENOMEM;
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}
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return 0;
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}
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void radeon_dummy_page_fini(struct radeon_device *rdev)
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{
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if (rdev->dummy_page.page == NULL)
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return;
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pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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__free_page(rdev->dummy_page.page);
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rdev->dummy_page.page = NULL;
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}
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/* ATOM accessor methods */
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static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = rdev->pll_rreg(rdev, reg);
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return r;
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}
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static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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rdev->pll_wreg(rdev, reg, val);
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}
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static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = rdev->mc_rreg(rdev, reg);
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return r;
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}
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static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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rdev->mc_wreg(rdev, reg, val);
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}
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static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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WREG32(reg*4, val);
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}
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static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
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{
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struct radeon_device *rdev = info->dev->dev_private;
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uint32_t r;
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r = RREG32(reg*4);
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return r;
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}
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int radeon_atombios_init(struct radeon_device *rdev)
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{
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struct card_info *atom_card_info =
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kzalloc(sizeof(struct card_info), GFP_KERNEL);
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if (!atom_card_info)
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return -ENOMEM;
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rdev->mode_info.atom_card_info = atom_card_info;
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atom_card_info->dev = rdev->ddev;
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atom_card_info->reg_read = cail_reg_read;
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atom_card_info->reg_write = cail_reg_write;
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atom_card_info->mc_read = cail_mc_read;
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atom_card_info->mc_write = cail_mc_write;
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atom_card_info->pll_read = cail_pll_read;
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atom_card_info->pll_write = cail_pll_write;
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rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
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mutex_init(&rdev->mode_info.atom_context->mutex);
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radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
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atom_allocate_fb_scratch(rdev->mode_info.atom_context);
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return 0;
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}
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void radeon_atombios_fini(struct radeon_device *rdev)
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{
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if (rdev->mode_info.atom_context) {
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kfree(rdev->mode_info.atom_context->scratch);
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kfree(rdev->mode_info.atom_context);
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}
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kfree(rdev->mode_info.atom_card_info);
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}
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int radeon_combios_init(struct radeon_device *rdev)
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{
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radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
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return 0;
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}
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void radeon_combios_fini(struct radeon_device *rdev)
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{
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}
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/* if we get transitioned to only one device, tak VGA back */
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static unsigned int radeon_vga_set_decode(void *cookie, bool state)
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{
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struct radeon_device *rdev = cookie;
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radeon_vga_set_state(rdev, state);
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if (state)
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return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
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VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
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else
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return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
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}
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void radeon_check_arguments(struct radeon_device *rdev)
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{
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/* vramlimit must be a power of two */
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switch (radeon_vram_limit) {
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case 0:
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|
case 4:
|
|
case 8:
|
|
case 16:
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
case 256:
|
|
case 512:
|
|
case 1024:
|
|
case 2048:
|
|
case 4096:
|
|
break;
|
|
default:
|
|
dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
|
|
radeon_vram_limit);
|
|
radeon_vram_limit = 0;
|
|
break;
|
|
}
|
|
radeon_vram_limit = radeon_vram_limit << 20;
|
|
/* gtt size must be power of two and greater or equal to 32M */
|
|
switch (radeon_gart_size) {
|
|
case 4:
|
|
case 8:
|
|
case 16:
|
|
dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
|
|
radeon_gart_size);
|
|
radeon_gart_size = 512;
|
|
break;
|
|
case 32:
|
|
case 64:
|
|
case 128:
|
|
case 256:
|
|
case 512:
|
|
case 1024:
|
|
case 2048:
|
|
case 4096:
|
|
break;
|
|
default:
|
|
dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
|
|
radeon_gart_size);
|
|
radeon_gart_size = 512;
|
|
break;
|
|
}
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
/* AGP mode can only be -1, 1, 2, 4, 8 */
|
|
switch (radeon_agpmode) {
|
|
case -1:
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
|
|
"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
|
|
radeon_agpmode = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
|
|
if (state == VGA_SWITCHEROO_ON) {
|
|
printk(KERN_INFO "radeon: switched on\n");
|
|
/* don't suspend or resume card normally */
|
|
rdev->powered_down = false;
|
|
radeon_resume_kms(dev);
|
|
drm_kms_helper_poll_enable(dev);
|
|
} else {
|
|
printk(KERN_INFO "radeon: switched off\n");
|
|
drm_kms_helper_poll_disable(dev);
|
|
radeon_suspend_kms(dev, pmm);
|
|
/* don't suspend or resume card normally */
|
|
rdev->powered_down = true;
|
|
}
|
|
}
|
|
|
|
static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
bool can_switch;
|
|
|
|
spin_lock(&dev->count_lock);
|
|
can_switch = (dev->open_count == 0);
|
|
spin_unlock(&dev->count_lock);
|
|
return can_switch;
|
|
}
|
|
|
|
|
|
int radeon_device_init(struct radeon_device *rdev,
|
|
struct drm_device *ddev,
|
|
struct pci_dev *pdev,
|
|
uint32_t flags)
|
|
{
|
|
int r;
|
|
int dma_bits;
|
|
|
|
rdev->shutdown = false;
|
|
rdev->dev = &pdev->dev;
|
|
rdev->ddev = ddev;
|
|
rdev->pdev = pdev;
|
|
rdev->flags = flags;
|
|
rdev->family = flags & RADEON_FAMILY_MASK;
|
|
rdev->is_atom_bios = false;
|
|
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
|
|
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
|
|
rdev->gpu_lockup = false;
|
|
rdev->accel_working = false;
|
|
|
|
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n",
|
|
radeon_family_name[rdev->family], pdev->vendor, pdev->device);
|
|
|
|
/* mutex initialization are all done here so we
|
|
* can recall function without having locking issues */
|
|
mutex_init(&rdev->cs_mutex);
|
|
mutex_init(&rdev->ib_pool.mutex);
|
|
mutex_init(&rdev->cp.mutex);
|
|
mutex_init(&rdev->dc_hw_i2c_mutex);
|
|
if (rdev->family >= CHIP_R600)
|
|
spin_lock_init(&rdev->ih.lock);
|
|
mutex_init(&rdev->gem.mutex);
|
|
mutex_init(&rdev->pm.mutex);
|
|
mutex_init(&rdev->vram_mutex);
|
|
rwlock_init(&rdev->fence_drv.lock);
|
|
INIT_LIST_HEAD(&rdev->gem.objects);
|
|
init_waitqueue_head(&rdev->irq.vblank_queue);
|
|
init_waitqueue_head(&rdev->irq.idle_queue);
|
|
|
|
/* setup workqueue */
|
|
rdev->wq = create_workqueue("radeon");
|
|
if (rdev->wq == NULL)
|
|
return -ENOMEM;
|
|
|
|
/* Set asic functions */
|
|
r = radeon_asic_init(rdev);
|
|
if (r)
|
|
return r;
|
|
radeon_check_arguments(rdev);
|
|
|
|
/* all of the newer IGP chips have an internal gart
|
|
* However some rs4xx report as AGP, so remove that here.
|
|
*/
|
|
if ((rdev->family >= CHIP_RS400) &&
|
|
(rdev->flags & RADEON_IS_IGP)) {
|
|
rdev->flags &= ~RADEON_IS_AGP;
|
|
}
|
|
|
|
if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
|
|
radeon_agp_disable(rdev);
|
|
}
|
|
|
|
/* set DMA mask + need_dma32 flags.
|
|
* PCIE - can handle 40-bits.
|
|
* IGP - can handle 40-bits (in theory)
|
|
* AGP - generally dma32 is safest
|
|
* PCI - only dma32
|
|
*/
|
|
rdev->need_dma32 = false;
|
|
if (rdev->flags & RADEON_IS_AGP)
|
|
rdev->need_dma32 = true;
|
|
if (rdev->flags & RADEON_IS_PCI)
|
|
rdev->need_dma32 = true;
|
|
|
|
dma_bits = rdev->need_dma32 ? 32 : 40;
|
|
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
|
|
if (r) {
|
|
printk(KERN_WARNING "radeon: No suitable DMA available.\n");
|
|
}
|
|
|
|
/* Registers mapping */
|
|
/* TODO: block userspace mapping of io register */
|
|
rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
|
|
rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
|
|
rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
|
|
if (rdev->rmmio == NULL) {
|
|
return -ENOMEM;
|
|
}
|
|
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
|
|
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
|
|
|
|
/* if we have > 1 VGA cards, then disable the radeon VGA resources */
|
|
/* this will fail for cards that aren't VGA class devices, just
|
|
* ignore it */
|
|
vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
|
|
vga_switcheroo_register_client(rdev->pdev,
|
|
radeon_switcheroo_set_state,
|
|
radeon_switcheroo_can_switch);
|
|
|
|
r = radeon_init(rdev);
|
|
if (r)
|
|
return r;
|
|
|
|
if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
|
|
/* Acceleration not working on AGP card try again
|
|
* with fallback to PCI or PCIE GART
|
|
*/
|
|
radeon_asic_reset(rdev);
|
|
radeon_fini(rdev);
|
|
radeon_agp_disable(rdev);
|
|
r = radeon_init(rdev);
|
|
if (r)
|
|
return r;
|
|
}
|
|
if (radeon_testing) {
|
|
radeon_test_moves(rdev);
|
|
}
|
|
if (radeon_benchmarking) {
|
|
radeon_benchmark(rdev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void radeon_device_fini(struct radeon_device *rdev)
|
|
{
|
|
DRM_INFO("radeon: finishing device.\n");
|
|
rdev->shutdown = true;
|
|
/* evict vram memory */
|
|
radeon_bo_evict_vram(rdev);
|
|
radeon_fini(rdev);
|
|
destroy_workqueue(rdev->wq);
|
|
vga_switcheroo_unregister_client(rdev->pdev);
|
|
vga_client_register(rdev->pdev, NULL, NULL, NULL);
|
|
iounmap(rdev->rmmio);
|
|
rdev->rmmio = NULL;
|
|
}
|
|
|
|
|
|
/*
|
|
* Suspend & resume.
|
|
*/
|
|
int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
|
|
{
|
|
struct radeon_device *rdev;
|
|
struct drm_crtc *crtc;
|
|
struct drm_connector *connector;
|
|
int r;
|
|
|
|
if (dev == NULL || dev->dev_private == NULL) {
|
|
return -ENODEV;
|
|
}
|
|
if (state.event == PM_EVENT_PRETHAW) {
|
|
return 0;
|
|
}
|
|
rdev = dev->dev_private;
|
|
|
|
if (rdev->powered_down)
|
|
return 0;
|
|
|
|
/* turn off display hw */
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
|
|
}
|
|
|
|
/* unpin the front buffers */
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
|
struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
|
|
struct radeon_bo *robj;
|
|
|
|
if (rfb == NULL || rfb->obj == NULL) {
|
|
continue;
|
|
}
|
|
robj = rfb->obj->driver_private;
|
|
/* don't unpin kernel fb objects */
|
|
if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
|
|
r = radeon_bo_reserve(robj, false);
|
|
if (r == 0) {
|
|
radeon_bo_unpin(robj);
|
|
radeon_bo_unreserve(robj);
|
|
}
|
|
}
|
|
}
|
|
/* evict vram memory */
|
|
radeon_bo_evict_vram(rdev);
|
|
/* wait for gpu to finish processing current batch */
|
|
radeon_fence_wait_last(rdev);
|
|
|
|
radeon_save_bios_scratch_regs(rdev);
|
|
|
|
radeon_pm_suspend(rdev);
|
|
radeon_suspend(rdev);
|
|
radeon_hpd_fini(rdev);
|
|
/* evict remaining vram memory */
|
|
radeon_bo_evict_vram(rdev);
|
|
|
|
radeon_agp_suspend(rdev);
|
|
|
|
pci_save_state(dev->pdev);
|
|
if (state.event == PM_EVENT_SUSPEND) {
|
|
/* Shut down the device */
|
|
pci_disable_device(dev->pdev);
|
|
pci_set_power_state(dev->pdev, PCI_D3hot);
|
|
}
|
|
acquire_console_sem();
|
|
radeon_fbdev_set_suspend(rdev, 1);
|
|
release_console_sem();
|
|
return 0;
|
|
}
|
|
|
|
int radeon_resume_kms(struct drm_device *dev)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
if (rdev->powered_down)
|
|
return 0;
|
|
|
|
acquire_console_sem();
|
|
pci_set_power_state(dev->pdev, PCI_D0);
|
|
pci_restore_state(dev->pdev);
|
|
if (pci_enable_device(dev->pdev)) {
|
|
release_console_sem();
|
|
return -1;
|
|
}
|
|
pci_set_master(dev->pdev);
|
|
/* resume AGP if in use */
|
|
radeon_agp_resume(rdev);
|
|
radeon_resume(rdev);
|
|
radeon_pm_resume(rdev);
|
|
radeon_restore_bios_scratch_regs(rdev);
|
|
radeon_fbdev_set_suspend(rdev, 0);
|
|
release_console_sem();
|
|
|
|
/* reset hpd state */
|
|
radeon_hpd_init(rdev);
|
|
/* blat the mode back in */
|
|
drm_helper_resume_force_mode(dev);
|
|
return 0;
|
|
}
|
|
|
|
int radeon_gpu_reset(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
radeon_save_bios_scratch_regs(rdev);
|
|
radeon_suspend(rdev);
|
|
|
|
r = radeon_asic_reset(rdev);
|
|
if (!r) {
|
|
dev_info(rdev->dev, "GPU reset succeed\n");
|
|
radeon_resume(rdev);
|
|
radeon_restore_bios_scratch_regs(rdev);
|
|
drm_helper_resume_force_mode(rdev->ddev);
|
|
return 0;
|
|
}
|
|
/* bad news, how to tell it to userspace ? */
|
|
dev_info(rdev->dev, "GPU reset failed\n");
|
|
return r;
|
|
}
|
|
|
|
|
|
/*
|
|
* Debugfs
|
|
*/
|
|
struct radeon_debugfs {
|
|
struct drm_info_list *files;
|
|
unsigned num_files;
|
|
};
|
|
static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
|
|
static unsigned _radeon_debugfs_count = 0;
|
|
|
|
int radeon_debugfs_add_files(struct radeon_device *rdev,
|
|
struct drm_info_list *files,
|
|
unsigned nfiles)
|
|
{
|
|
unsigned i;
|
|
|
|
for (i = 0; i < _radeon_debugfs_count; i++) {
|
|
if (_radeon_debugfs[i].files == files) {
|
|
/* Already registered */
|
|
return 0;
|
|
}
|
|
}
|
|
if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
|
|
DRM_ERROR("Reached maximum number of debugfs files.\n");
|
|
DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
|
|
return -EINVAL;
|
|
}
|
|
_radeon_debugfs[_radeon_debugfs_count].files = files;
|
|
_radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
|
|
_radeon_debugfs_count++;
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
drm_debugfs_create_files(files, nfiles,
|
|
rdev->ddev->control->debugfs_root,
|
|
rdev->ddev->control);
|
|
drm_debugfs_create_files(files, nfiles,
|
|
rdev->ddev->primary->debugfs_root,
|
|
rdev->ddev->primary);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
int radeon_debugfs_init(struct drm_minor *minor)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void radeon_debugfs_cleanup(struct drm_minor *minor)
|
|
{
|
|
unsigned i;
|
|
|
|
for (i = 0; i < _radeon_debugfs_count; i++) {
|
|
drm_debugfs_remove_files(_radeon_debugfs[i].files,
|
|
_radeon_debugfs[i].num_files, minor);
|
|
}
|
|
}
|
|
#endif
|