99 lines
2.7 KiB
ArmAsm
99 lines
2.7 KiB
ArmAsm
/*
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* Based on arch/arm/mm/proc-macros.S
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*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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/*
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* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
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*/
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.macro vma_vm_mm, rd, rn
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ldr \rd, [\rn, #VMA_VM_MM]
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.endm
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/*
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* mmid - get context id from mm pointer (mm->context.id)
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*/
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.macro mmid, rd, rn
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ldr \rd, [\rn, #MM_CONTEXT_ID]
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.endm
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/*
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* dcache_line_size - get the minimum D-cache line size from the CTR register.
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*/
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.macro dcache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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ubfm \tmp, \tmp, #16, #19 // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* icache_line_size - get the minimum I-cache line size from the CTR register.
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*/
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.macro icache_line_size, reg, tmp
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mrs \tmp, ctr_el0 // read CTR
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and \tmp, \tmp, #0xf // cache line size encoding
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mov \reg, #4 // bytes per word
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lsl \reg, \reg, \tmp // actual cache line size
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.endm
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/*
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* tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
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*/
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.macro tcr_set_idmap_t0sz, valreg, tmpreg
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#ifndef CONFIG_ARM64_VA_BITS_48
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ldr_l \tmpreg, idmap_t0sz
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bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
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#endif
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.endm
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/*
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* Macro to perform a data cache maintenance for the interval
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* [kaddr, kaddr + size)
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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* kaddr: starting virtual address of the region
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* size: size of the region
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* Corrupts: kaddr, size, tmp1, tmp2
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*/
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.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
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dcache_line_size \tmp1, \tmp2
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add \size, \kaddr, \size
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sub \tmp2, \tmp1, #1
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bic \kaddr, \kaddr, \tmp2
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9998: dc \op, \kaddr
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add \kaddr, \kaddr, \tmp1
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cmp \kaddr, \size
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b.lo 9998b
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dsb \domain
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.endm
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/*
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* reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
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*/
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.macro reset_pmuserenr_el0, tmpreg
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mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer
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sbfx \tmpreg, \tmpreg, #8, #4
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cmp \tmpreg, #1 // Skip if no PMU present
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b.lt 9000f
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msr pmuserenr_el0, xzr // Disable PMU access from EL0
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9000:
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.endm
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