558 lines
13 KiB
C
558 lines
13 KiB
C
/*
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* Analog devices AD5360, AD5361, AD5362, AD5363, AD5370, AD5371, AD5373
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* multi-channel Digital to Analog Converters driver
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*
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* Copyright 2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2.
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spi/spi.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/regulator/consumer.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#define AD5360_CMD(x) ((x) << 22)
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#define AD5360_ADDR(x) ((x) << 16)
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#define AD5360_READBACK_TYPE(x) ((x) << 13)
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#define AD5360_READBACK_ADDR(x) ((x) << 7)
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#define AD5360_CHAN_ADDR(chan) ((chan) + 0x8)
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#define AD5360_CMD_WRITE_DATA 0x3
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#define AD5360_CMD_WRITE_OFFSET 0x2
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#define AD5360_CMD_WRITE_GAIN 0x1
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#define AD5360_CMD_SPECIAL_FUNCTION 0x0
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/* Special function register addresses */
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#define AD5360_REG_SF_NOP 0x0
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#define AD5360_REG_SF_CTRL 0x1
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#define AD5360_REG_SF_OFS(x) (0x2 + (x))
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#define AD5360_REG_SF_READBACK 0x5
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#define AD5360_SF_CTRL_PWR_DOWN BIT(0)
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#define AD5360_READBACK_X1A 0x0
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#define AD5360_READBACK_X1B 0x1
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#define AD5360_READBACK_OFFSET 0x2
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#define AD5360_READBACK_GAIN 0x3
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#define AD5360_READBACK_SF 0x4
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/**
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* struct ad5360_chip_info - chip specific information
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* @channel_template: channel specification template
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* @num_channels: number of channels
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* @channels_per_group: number of channels per group
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* @num_vrefs: number of vref supplies for the chip
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*/
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struct ad5360_chip_info {
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struct iio_chan_spec channel_template;
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unsigned int num_channels;
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unsigned int channels_per_group;
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unsigned int num_vrefs;
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};
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/**
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* struct ad5360_state - driver instance specific data
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* @spi: spi_device
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* @chip_info: chip model specific constants, available modes etc
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* @vref_reg: vref supply regulators
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* @ctrl: control register cache
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* @data: spi transfer buffers
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*/
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struct ad5360_state {
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struct spi_device *spi;
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const struct ad5360_chip_info *chip_info;
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struct regulator_bulk_data vref_reg[3];
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unsigned int ctrl;
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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union {
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__be32 d32;
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u8 d8[4];
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} data[2] ____cacheline_aligned;
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};
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enum ad5360_type {
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ID_AD5360,
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ID_AD5361,
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ID_AD5362,
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ID_AD5363,
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ID_AD5370,
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ID_AD5371,
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ID_AD5372,
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ID_AD5373,
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};
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#define AD5360_CHANNEL(bits) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.output = 1, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_OFFSET) | \
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BIT(IIO_CHAN_INFO_CALIBSCALE) | \
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BIT(IIO_CHAN_INFO_CALIBBIAS), \
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.scan_type = IIO_ST('u', (bits), 16, 16 - (bits)) \
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}
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static const struct ad5360_chip_info ad5360_chip_info_tbl[] = {
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[ID_AD5360] = {
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.channel_template = AD5360_CHANNEL(16),
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.num_channels = 16,
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.channels_per_group = 8,
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.num_vrefs = 2,
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},
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[ID_AD5361] = {
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.channel_template = AD5360_CHANNEL(14),
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.num_channels = 16,
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.channels_per_group = 8,
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.num_vrefs = 2,
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},
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[ID_AD5362] = {
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.channel_template = AD5360_CHANNEL(16),
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.num_channels = 8,
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.channels_per_group = 4,
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.num_vrefs = 2,
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},
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[ID_AD5363] = {
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.channel_template = AD5360_CHANNEL(14),
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.num_channels = 8,
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.channels_per_group = 4,
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.num_vrefs = 2,
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},
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[ID_AD5370] = {
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.channel_template = AD5360_CHANNEL(16),
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.num_channels = 40,
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.channels_per_group = 8,
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.num_vrefs = 2,
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},
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[ID_AD5371] = {
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.channel_template = AD5360_CHANNEL(14),
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.num_channels = 40,
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.channels_per_group = 8,
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.num_vrefs = 3,
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},
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[ID_AD5372] = {
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.channel_template = AD5360_CHANNEL(16),
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.num_channels = 32,
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.channels_per_group = 8,
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.num_vrefs = 2,
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},
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[ID_AD5373] = {
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.channel_template = AD5360_CHANNEL(14),
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.num_channels = 32,
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.channels_per_group = 8,
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.num_vrefs = 2,
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},
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};
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static unsigned int ad5360_get_channel_vref_index(struct ad5360_state *st,
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unsigned int channel)
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{
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unsigned int i;
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/* The first groups have their own vref, while the remaining groups
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* share the last vref */
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i = channel / st->chip_info->channels_per_group;
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if (i >= st->chip_info->num_vrefs)
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i = st->chip_info->num_vrefs - 1;
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return i;
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}
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static int ad5360_get_channel_vref(struct ad5360_state *st,
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unsigned int channel)
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{
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unsigned int i = ad5360_get_channel_vref_index(st, channel);
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return regulator_get_voltage(st->vref_reg[i].consumer);
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}
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static int ad5360_write_unlocked(struct iio_dev *indio_dev,
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unsigned int cmd, unsigned int addr, unsigned int val,
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unsigned int shift)
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{
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struct ad5360_state *st = iio_priv(indio_dev);
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val <<= shift;
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val |= AD5360_CMD(cmd) | AD5360_ADDR(addr);
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st->data[0].d32 = cpu_to_be32(val);
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return spi_write(st->spi, &st->data[0].d8[1], 3);
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}
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static int ad5360_write(struct iio_dev *indio_dev, unsigned int cmd,
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unsigned int addr, unsigned int val, unsigned int shift)
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{
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int ret;
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mutex_lock(&indio_dev->mlock);
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ret = ad5360_write_unlocked(indio_dev, cmd, addr, val, shift);
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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static int ad5360_read(struct iio_dev *indio_dev, unsigned int type,
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unsigned int addr)
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{
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struct ad5360_state *st = iio_priv(indio_dev);
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int ret;
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struct spi_transfer t[] = {
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{
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.tx_buf = &st->data[0].d8[1],
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.len = 3,
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.cs_change = 1,
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}, {
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.rx_buf = &st->data[1].d8[1],
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.len = 3,
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},
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};
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mutex_lock(&indio_dev->mlock);
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st->data[0].d32 = cpu_to_be32(AD5360_CMD(AD5360_CMD_SPECIAL_FUNCTION) |
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AD5360_ADDR(AD5360_REG_SF_READBACK) |
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AD5360_READBACK_TYPE(type) |
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AD5360_READBACK_ADDR(addr));
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ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
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if (ret >= 0)
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ret = be32_to_cpu(st->data[1].d32) & 0xffff;
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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static ssize_t ad5360_read_dac_powerdown(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad5360_state *st = iio_priv(indio_dev);
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return sprintf(buf, "%d\n", (bool)(st->ctrl & AD5360_SF_CTRL_PWR_DOWN));
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}
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static int ad5360_update_ctrl(struct iio_dev *indio_dev, unsigned int set,
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unsigned int clr)
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{
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struct ad5360_state *st = iio_priv(indio_dev);
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unsigned int ret;
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mutex_lock(&indio_dev->mlock);
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st->ctrl |= set;
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st->ctrl &= ~clr;
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ret = ad5360_write_unlocked(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
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AD5360_REG_SF_CTRL, st->ctrl, 0);
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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static ssize_t ad5360_write_dac_powerdown(struct device *dev,
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struct device_attribute *attr, const char *buf, size_t len)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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bool pwr_down;
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int ret;
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ret = strtobool(buf, &pwr_down);
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if (ret)
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return ret;
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if (pwr_down)
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ret = ad5360_update_ctrl(indio_dev, AD5360_SF_CTRL_PWR_DOWN, 0);
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else
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ret = ad5360_update_ctrl(indio_dev, 0, AD5360_SF_CTRL_PWR_DOWN);
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return ret ? ret : len;
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}
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static IIO_DEVICE_ATTR(out_voltage_powerdown,
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S_IRUGO | S_IWUSR,
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ad5360_read_dac_powerdown,
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ad5360_write_dac_powerdown, 0);
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static struct attribute *ad5360_attributes[] = {
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&iio_dev_attr_out_voltage_powerdown.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group ad5360_attribute_group = {
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.attrs = ad5360_attributes,
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};
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static int ad5360_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val,
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int val2,
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long mask)
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{
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struct ad5360_state *st = iio_priv(indio_dev);
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int max_val = (1 << chan->scan_type.realbits);
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unsigned int ofs_index;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (val >= max_val || val < 0)
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return -EINVAL;
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return ad5360_write(indio_dev, AD5360_CMD_WRITE_DATA,
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chan->address, val, chan->scan_type.shift);
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case IIO_CHAN_INFO_CALIBBIAS:
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if (val >= max_val || val < 0)
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return -EINVAL;
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return ad5360_write(indio_dev, AD5360_CMD_WRITE_OFFSET,
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chan->address, val, chan->scan_type.shift);
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case IIO_CHAN_INFO_CALIBSCALE:
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if (val >= max_val || val < 0)
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return -EINVAL;
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return ad5360_write(indio_dev, AD5360_CMD_WRITE_GAIN,
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chan->address, val, chan->scan_type.shift);
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case IIO_CHAN_INFO_OFFSET:
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if (val <= -max_val || val > 0)
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return -EINVAL;
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val = -val;
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/* offset is supposed to have the same scale as raw, but it
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* is always 14bits wide, so on a chip where the raw value has
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* more bits, we need to shift offset. */
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val >>= (chan->scan_type.realbits - 14);
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/* There is one DAC offset register per vref. Changing one
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* channels offset will also change the offset for all other
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* channels which share the same vref supply. */
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ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
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return ad5360_write(indio_dev, AD5360_CMD_SPECIAL_FUNCTION,
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AD5360_REG_SF_OFS(ofs_index), val, 0);
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default:
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break;
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}
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return -EINVAL;
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}
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static int ad5360_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long m)
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{
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struct ad5360_state *st = iio_priv(indio_dev);
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unsigned int ofs_index;
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int scale_uv;
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int ret;
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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ret = ad5360_read(indio_dev, AD5360_READBACK_X1A,
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chan->address);
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if (ret < 0)
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return ret;
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*val = ret >> chan->scan_type.shift;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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scale_uv = ad5360_get_channel_vref(st, chan->channel);
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if (scale_uv < 0)
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return scale_uv;
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/* vout = 4 * vref * dac_code */
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*val = scale_uv * 4 / 1000;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_CHAN_INFO_CALIBBIAS:
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ret = ad5360_read(indio_dev, AD5360_READBACK_OFFSET,
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chan->address);
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if (ret < 0)
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return ret;
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*val = ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_CALIBSCALE:
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ret = ad5360_read(indio_dev, AD5360_READBACK_GAIN,
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chan->address);
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if (ret < 0)
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return ret;
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*val = ret;
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_OFFSET:
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ofs_index = ad5360_get_channel_vref_index(st, chan->channel);
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ret = ad5360_read(indio_dev, AD5360_READBACK_SF,
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AD5360_REG_SF_OFS(ofs_index));
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if (ret < 0)
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return ret;
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ret <<= (chan->scan_type.realbits - 14);
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*val = -ret;
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return IIO_VAL_INT;
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}
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return -EINVAL;
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}
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static const struct iio_info ad5360_info = {
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.read_raw = ad5360_read_raw,
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.write_raw = ad5360_write_raw,
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.attrs = &ad5360_attribute_group,
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.driver_module = THIS_MODULE,
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};
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static const char * const ad5360_vref_name[] = {
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"vref0", "vref1", "vref2"
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};
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static int ad5360_alloc_channels(struct iio_dev *indio_dev)
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{
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struct ad5360_state *st = iio_priv(indio_dev);
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struct iio_chan_spec *channels;
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unsigned int i;
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channels = kcalloc(st->chip_info->num_channels,
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sizeof(struct iio_chan_spec), GFP_KERNEL);
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if (!channels)
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return -ENOMEM;
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for (i = 0; i < st->chip_info->num_channels; ++i) {
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channels[i] = st->chip_info->channel_template;
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channels[i].channel = i;
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channels[i].address = AD5360_CHAN_ADDR(i);
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}
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indio_dev->channels = channels;
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return 0;
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}
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static int ad5360_probe(struct spi_device *spi)
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{
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enum ad5360_type type = spi_get_device_id(spi)->driver_data;
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struct iio_dev *indio_dev;
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struct ad5360_state *st;
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unsigned int i;
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int ret;
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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if (indio_dev == NULL) {
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dev_err(&spi->dev, "Failed to allocate iio device\n");
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return -ENOMEM;
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}
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st = iio_priv(indio_dev);
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spi_set_drvdata(spi, indio_dev);
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st->chip_info = &ad5360_chip_info_tbl[type];
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st->spi = spi;
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indio_dev->dev.parent = &spi->dev;
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indio_dev->name = spi_get_device_id(spi)->name;
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indio_dev->info = &ad5360_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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indio_dev->num_channels = st->chip_info->num_channels;
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ret = ad5360_alloc_channels(indio_dev);
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if (ret) {
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dev_err(&spi->dev, "Failed to allocate channel spec: %d\n", ret);
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return ret;
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}
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for (i = 0; i < st->chip_info->num_vrefs; ++i)
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st->vref_reg[i].supply = ad5360_vref_name[i];
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ret = devm_regulator_bulk_get(&st->spi->dev, st->chip_info->num_vrefs,
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st->vref_reg);
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if (ret) {
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dev_err(&spi->dev, "Failed to request vref regulators: %d\n", ret);
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goto error_free_channels;
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}
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ret = regulator_bulk_enable(st->chip_info->num_vrefs, st->vref_reg);
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if (ret) {
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dev_err(&spi->dev, "Failed to enable vref regulators: %d\n", ret);
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goto error_free_channels;
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}
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ret = iio_device_register(indio_dev);
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if (ret) {
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dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
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goto error_disable_reg;
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}
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|
|
|
return 0;
|
|
|
|
error_disable_reg:
|
|
regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
|
|
error_free_channels:
|
|
kfree(indio_dev->channels);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ad5360_remove(struct spi_device *spi)
|
|
{
|
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
|
struct ad5360_state *st = iio_priv(indio_dev);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
kfree(indio_dev->channels);
|
|
|
|
regulator_bulk_disable(st->chip_info->num_vrefs, st->vref_reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_device_id ad5360_ids[] = {
|
|
{ "ad5360", ID_AD5360 },
|
|
{ "ad5361", ID_AD5361 },
|
|
{ "ad5362", ID_AD5362 },
|
|
{ "ad5363", ID_AD5363 },
|
|
{ "ad5370", ID_AD5370 },
|
|
{ "ad5371", ID_AD5371 },
|
|
{ "ad5372", ID_AD5372 },
|
|
{ "ad5373", ID_AD5373 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(spi, ad5360_ids);
|
|
|
|
static struct spi_driver ad5360_driver = {
|
|
.driver = {
|
|
.name = "ad5360",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = ad5360_probe,
|
|
.remove = ad5360_remove,
|
|
.id_table = ad5360_ids,
|
|
};
|
|
module_spi_driver(ad5360_driver);
|
|
|
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
|
MODULE_DESCRIPTION("Analog Devices AD5360/61/62/63/70/71/72/73 DAC");
|
|
MODULE_LICENSE("GPL v2");
|