1026 lines
29 KiB
C
1026 lines
29 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* core.c - DesignWare HS OTG Controller common routines
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*
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* Copyright (C) 2004-2013 Synopsys, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* The Core code provides basic services for accessing and managing the
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* DWC_otg hardware. These services are used by both the Host Controller
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* Driver and the Peripheral Controller Driver.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/ch11.h>
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#include "core.h"
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#include "hcd.h"
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/**
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* dwc2_backup_global_registers() - Backup global controller registers.
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* When suspending usb bus, registers needs to be backuped
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* if controller power is disabled once suspended.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Backup global regs */
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gr = &hsotg->gr_backup;
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gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
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gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
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gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
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gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
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gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
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gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
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gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
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gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
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gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
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gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
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gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
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gr->valid = true;
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return 0;
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}
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/**
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* dwc2_restore_global_registers() - Restore controller global registers.
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* When resuming usb bus, device registers needs to be restored
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* if controller power were disabled.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
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{
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struct dwc2_gregs_backup *gr;
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dev_dbg(hsotg->dev, "%s\n", __func__);
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/* Restore global regs */
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gr = &hsotg->gr_backup;
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if (!gr->valid) {
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dev_err(hsotg->dev, "%s: no global registers to restore\n",
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__func__);
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return -EINVAL;
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}
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gr->valid = false;
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dwc2_writel(hsotg, 0xffffffff, GINTSTS);
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dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
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dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
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dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
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dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
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dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
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dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
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dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
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dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
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dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
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dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
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dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
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return 0;
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}
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/**
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* dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @restore: Controller registers need to be restored
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*/
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int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
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{
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u32 pcgcctl;
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int ret = 0;
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if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
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return -ENOTSUPP;
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pcgcctl = dwc2_readl(hsotg, PCGCTL);
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pcgcctl &= ~PCGCTL_STOPPCLK;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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pcgcctl = dwc2_readl(hsotg, PCGCTL);
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pcgcctl &= ~PCGCTL_PWRCLMP;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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pcgcctl = dwc2_readl(hsotg, PCGCTL);
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pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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udelay(100);
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if (restore) {
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ret = dwc2_restore_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_restore_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_restore_device_registers(hsotg, 0);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to restore device registers\n",
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__func__);
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return ret;
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}
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}
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}
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return ret;
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}
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/**
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* dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
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*
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* @hsotg: Programming view of the DWC_otg controller
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*/
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int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
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{
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u32 pcgcctl;
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int ret = 0;
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if (!hsotg->params.power_down)
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return -ENOTSUPP;
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/* Backup all registers */
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ret = dwc2_backup_global_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup global registers\n",
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__func__);
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return ret;
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}
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if (dwc2_is_host_mode(hsotg)) {
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ret = dwc2_backup_host_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup host registers\n",
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__func__);
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return ret;
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}
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} else {
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ret = dwc2_backup_device_registers(hsotg);
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if (ret) {
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dev_err(hsotg->dev, "%s: failed to backup device registers\n",
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__func__);
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return ret;
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}
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}
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/*
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* Clear any pending interrupts since dwc2 will not be able to
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* clear them after entering partial_power_down.
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*/
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dwc2_writel(hsotg, 0xffffffff, GINTSTS);
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/* Put the controller in low power state */
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pcgcctl = dwc2_readl(hsotg, PCGCTL);
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pcgcctl |= PCGCTL_PWRCLMP;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_RSTPDWNMODULE;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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ndelay(20);
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pcgcctl |= PCGCTL_STOPPCLK;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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return ret;
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}
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/**
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* dwc2_restore_essential_regs() - Restore essiential regs of core.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @rmode: Restore mode, enabled in case of remote-wakeup.
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* @is_host: Host or device mode.
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*/
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static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
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int is_host)
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{
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u32 pcgcctl;
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struct dwc2_gregs_backup *gr;
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struct dwc2_dregs_backup *dr;
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struct dwc2_hregs_backup *hr;
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gr = &hsotg->gr_backup;
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dr = &hsotg->dr_backup;
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hr = &hsotg->hr_backup;
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dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
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/* Load restore values for [31:14] bits */
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pcgcctl = (gr->pcgcctl & 0xffffc000);
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/* If High Speed */
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if (is_host) {
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if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
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pcgcctl |= BIT(17);
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} else {
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if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
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pcgcctl |= BIT(17);
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}
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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/* Umnask global Interrupt in GAHBCFG and restore it */
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dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
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/* Clear all pending interupts */
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dwc2_writel(hsotg, 0xffffffff, GINTSTS);
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/* Unmask restore done interrupt */
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dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
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/* Restore GUSBCFG and HCFG/DCFG */
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dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
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if (is_host) {
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dwc2_writel(hsotg, hr->hcfg, HCFG);
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if (rmode)
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pcgcctl |= PCGCTL_RESTOREMODE;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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udelay(10);
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pcgcctl |= PCGCTL_ESS_REG_RESTORED;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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udelay(10);
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} else {
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dwc2_writel(hsotg, dr->dcfg, DCFG);
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if (!rmode)
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pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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udelay(10);
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pcgcctl |= PCGCTL_ESS_REG_RESTORED;
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dwc2_writel(hsotg, pcgcctl, PCGCTL);
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udelay(10);
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}
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}
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/**
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* dwc2_hib_restore_common() - Common part of restore routine.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
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* @is_host: Host or device mode.
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*/
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void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
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int is_host)
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{
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u32 gpwrdn;
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/* Switch-on voltage to the core */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_PWRDNSWTCH;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Reset core */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_PWRDNRSTN;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Enable restore from PMU */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn |= GPWRDN_RESTORE;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Disable Power Down Clamp */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_PWRDNCLMP;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(50);
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if (!is_host && rem_wakeup)
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udelay(70);
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/* Deassert reset core */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn |= GPWRDN_PWRDNRSTN;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Disable PMU interrupt */
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gpwrdn = dwc2_readl(hsotg, GPWRDN);
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gpwrdn &= ~GPWRDN_PMUINTSEL;
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dwc2_writel(hsotg, gpwrdn, GPWRDN);
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udelay(10);
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/* Set Restore Essential Regs bit in PCGCCTL register */
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dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
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/*
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* Wait For Restore_done Interrupt. This mechanism of polling the
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* interrupt is introduced to avoid any possible race conditions
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*/
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if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
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20000)) {
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dev_dbg(hsotg->dev,
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"%s: Restore Done wan't generated here\n",
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__func__);
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} else {
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dev_dbg(hsotg->dev, "restore done generated here\n");
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}
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}
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/**
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* dwc2_wait_for_mode() - Waits for the controller mode.
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* @hsotg: Programming view of the DWC_otg controller.
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* @host_mode: If true, waits for host mode, otherwise device mode.
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*/
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static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
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bool host_mode)
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{
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ktime_t start;
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ktime_t end;
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unsigned int timeout = 110;
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dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
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host_mode ? "host" : "device");
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start = ktime_get();
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while (1) {
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s64 ms;
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if (dwc2_is_host_mode(hsotg) == host_mode) {
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dev_vdbg(hsotg->dev, "%s mode set\n",
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host_mode ? "Host" : "Device");
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break;
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}
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end = ktime_get();
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ms = ktime_to_ms(ktime_sub(end, start));
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if (ms >= (s64)timeout) {
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dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
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__func__, host_mode ? "host" : "device");
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break;
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}
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usleep_range(1000, 2000);
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}
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}
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/**
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* dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
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* filter is enabled.
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*
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* @hsotg: Programming view of DWC_otg controller
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*/
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static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
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{
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u32 gsnpsid;
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u32 ghwcfg4;
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if (!dwc2_hw_is_otg(hsotg))
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return false;
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/* Check if core configuration includes the IDDIG filter. */
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ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
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if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
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return false;
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/*
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* Check if the IDDIG debounce filter is bypassed. Available
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* in core version >= 3.10a.
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*/
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gsnpsid = dwc2_readl(hsotg, GSNPSID);
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if (gsnpsid >= DWC2_CORE_REV_3_10a) {
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u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
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if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
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return false;
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}
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return true;
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}
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/*
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* dwc2_enter_hibernation() - Common function to enter hibernation.
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*
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* @hsotg: Programming view of the DWC_otg controller
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* @is_host: True if core is in host mode.
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*
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* Return: 0 if successful, negative error code otherwise
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*/
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int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
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{
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if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_HIBERNATION)
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return -ENOTSUPP;
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if (is_host)
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return dwc2_host_enter_hibernation(hsotg);
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else
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return dwc2_gadget_enter_hibernation(hsotg);
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}
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/*
|
|
* dwc2_exit_hibernation() - Common function to exit from hibernation.
|
|
*
|
|
* @hsotg: Programming view of the DWC_otg controller
|
|
* @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
|
|
* @reset: Enabled in case of restore with reset.
|
|
* @is_host: True if core is in host mode.
|
|
*
|
|
* Return: 0 if successful, negative error code otherwise
|
|
*/
|
|
int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
|
|
int reset, int is_host)
|
|
{
|
|
if (is_host)
|
|
return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
|
|
else
|
|
return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
|
|
}
|
|
|
|
/*
|
|
* Do core a soft reset of the core. Be careful with this because it
|
|
* resets all the internal state machines of the core.
|
|
*/
|
|
int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
|
|
{
|
|
u32 greset;
|
|
bool wait_for_host_mode = false;
|
|
|
|
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
/*
|
|
* If the current mode is host, either due to the force mode
|
|
* bit being set (which persists after core reset) or the
|
|
* connector id pin, a core soft reset will temporarily reset
|
|
* the mode to device. A delay from the IDDIG debounce filter
|
|
* will occur before going back to host mode.
|
|
*
|
|
* Determine whether we will go back into host mode after a
|
|
* reset and account for this delay after the reset.
|
|
*/
|
|
if (dwc2_iddig_filter_enabled(hsotg)) {
|
|
u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
|
|
u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
|
|
|
|
if (!(gotgctl & GOTGCTL_CONID_B) ||
|
|
(gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
|
|
wait_for_host_mode = true;
|
|
}
|
|
}
|
|
|
|
/* Core Soft Reset */
|
|
greset = dwc2_readl(hsotg, GRSTCTL);
|
|
greset |= GRSTCTL_CSFTRST;
|
|
dwc2_writel(hsotg, greset, GRSTCTL);
|
|
|
|
if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
|
|
dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
|
|
__func__);
|
|
return -EBUSY;
|
|
}
|
|
|
|
/* Wait for AHB master IDLE state */
|
|
if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 50)) {
|
|
dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
|
|
__func__);
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (wait_for_host_mode && !skip_wait)
|
|
dwc2_wait_for_mode(hsotg, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* dwc2_force_mode() - Force the mode of the controller.
|
|
*
|
|
* Forcing the mode is needed for two cases:
|
|
*
|
|
* 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
|
|
* controller to stay in a particular mode regardless of ID pin
|
|
* changes. We do this once during probe.
|
|
*
|
|
* 2) During probe we want to read reset values of the hw
|
|
* configuration registers that are only available in either host or
|
|
* device mode. We may need to force the mode if the current mode does
|
|
* not allow us to access the register in the mode that we want.
|
|
*
|
|
* In either case it only makes sense to force the mode if the
|
|
* controller hardware is OTG capable.
|
|
*
|
|
* Checks are done in this function to determine whether doing a force
|
|
* would be valid or not.
|
|
*
|
|
* If a force is done, it requires a IDDIG debounce filter delay if
|
|
* the filter is configured and enabled. We poll the current mode of
|
|
* the controller to account for this delay.
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
* @host: Host mode flag
|
|
*/
|
|
void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
|
|
{
|
|
u32 gusbcfg;
|
|
u32 set;
|
|
u32 clear;
|
|
|
|
dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
|
|
|
|
/*
|
|
* Force mode has no effect if the hardware is not OTG.
|
|
*/
|
|
if (!dwc2_hw_is_otg(hsotg))
|
|
return;
|
|
|
|
/*
|
|
* If dr_mode is either peripheral or host only, there is no
|
|
* need to ever force the mode to the opposite mode.
|
|
*/
|
|
if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
|
|
return;
|
|
|
|
if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
|
|
return;
|
|
|
|
gusbcfg = dwc2_readl(hsotg, GUSBCFG);
|
|
|
|
set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
|
|
clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
|
|
|
|
gusbcfg &= ~clear;
|
|
gusbcfg |= set;
|
|
dwc2_writel(hsotg, gusbcfg, GUSBCFG);
|
|
|
|
dwc2_wait_for_mode(hsotg, host);
|
|
return;
|
|
}
|
|
|
|
/**
|
|
* dwc2_clear_force_mode() - Clears the force mode bits.
|
|
*
|
|
* After clearing the bits, wait up to 100 ms to account for any
|
|
* potential IDDIG filter delay. We can't know if we expect this delay
|
|
* or not because the value of the connector ID status is affected by
|
|
* the force mode. We only need to call this once during probe if
|
|
* dr_mode == OTG.
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 gusbcfg;
|
|
|
|
if (!dwc2_hw_is_otg(hsotg))
|
|
return;
|
|
|
|
dev_dbg(hsotg->dev, "Clearing force mode bits\n");
|
|
|
|
gusbcfg = dwc2_readl(hsotg, GUSBCFG);
|
|
gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
|
|
gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
|
|
dwc2_writel(hsotg, gusbcfg, GUSBCFG);
|
|
|
|
if (dwc2_iddig_filter_enabled(hsotg))
|
|
msleep(100);
|
|
}
|
|
|
|
/*
|
|
* Sets or clears force mode based on the dr_mode parameter.
|
|
*/
|
|
void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
|
|
{
|
|
switch (hsotg->dr_mode) {
|
|
case USB_DR_MODE_HOST:
|
|
/*
|
|
* NOTE: This is required for some rockchip soc based
|
|
* platforms on their host-only dwc2.
|
|
*/
|
|
if (!dwc2_hw_is_otg(hsotg))
|
|
msleep(50);
|
|
|
|
break;
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
dwc2_force_mode(hsotg, false);
|
|
break;
|
|
case USB_DR_MODE_OTG:
|
|
dwc2_clear_force_mode(hsotg);
|
|
break;
|
|
default:
|
|
dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
|
|
__func__, hsotg->dr_mode);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* dwc2_enable_acg - enable active clock gating feature
|
|
*/
|
|
void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
|
|
{
|
|
if (hsotg->params.acg_enable) {
|
|
u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
|
|
|
|
dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
|
|
pcgcctl1 |= PCGCCTL1_GATEEN;
|
|
dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* dwc2_dump_host_registers() - Prints the host registers
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*
|
|
* NOTE: This function will be removed once the peripheral controller code
|
|
* is integrated and the driver is stable
|
|
*/
|
|
void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
|
|
{
|
|
#ifdef DEBUG
|
|
u32 __iomem *addr;
|
|
int i;
|
|
|
|
dev_dbg(hsotg->dev, "Host Global Registers\n");
|
|
addr = hsotg->regs + HCFG;
|
|
dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HCFG));
|
|
addr = hsotg->regs + HFIR;
|
|
dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HFIR));
|
|
addr = hsotg->regs + HFNUM;
|
|
dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HFNUM));
|
|
addr = hsotg->regs + HPTXSTS;
|
|
dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
|
|
addr = hsotg->regs + HAINT;
|
|
dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HAINT));
|
|
addr = hsotg->regs + HAINTMSK;
|
|
dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
|
|
if (hsotg->params.dma_desc_enable) {
|
|
addr = hsotg->regs + HFLBADDR;
|
|
dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
|
|
}
|
|
|
|
addr = hsotg->regs + HPRT0;
|
|
dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HPRT0));
|
|
|
|
for (i = 0; i < hsotg->params.host_channels; i++) {
|
|
dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
|
|
addr = hsotg->regs + HCCHAR(i);
|
|
dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
|
|
addr = hsotg->regs + HCSPLT(i);
|
|
dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
|
|
addr = hsotg->regs + HCINT(i);
|
|
dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
|
|
addr = hsotg->regs + HCINTMSK(i);
|
|
dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
|
|
addr = hsotg->regs + HCTSIZ(i);
|
|
dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
|
|
addr = hsotg->regs + HCDMA(i);
|
|
dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
|
|
if (hsotg->params.dma_desc_enable) {
|
|
addr = hsotg->regs + HCDMAB(i);
|
|
dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg,
|
|
HCDMAB(i)));
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* dwc2_dump_global_registers() - Prints the core global registers
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*
|
|
* NOTE: This function will be removed once the peripheral controller code
|
|
* is integrated and the driver is stable
|
|
*/
|
|
void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
|
|
{
|
|
#ifdef DEBUG
|
|
u32 __iomem *addr;
|
|
|
|
dev_dbg(hsotg->dev, "Core Global Registers\n");
|
|
addr = hsotg->regs + GOTGCTL;
|
|
dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
|
|
addr = hsotg->regs + GOTGINT;
|
|
dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
|
|
addr = hsotg->regs + GAHBCFG;
|
|
dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
|
|
addr = hsotg->regs + GUSBCFG;
|
|
dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
|
|
addr = hsotg->regs + GRSTCTL;
|
|
dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
|
|
addr = hsotg->regs + GINTSTS;
|
|
dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
|
|
addr = hsotg->regs + GINTMSK;
|
|
dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
|
|
addr = hsotg->regs + GRXSTSR;
|
|
dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
|
|
addr = hsotg->regs + GRXFSIZ;
|
|
dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
|
|
addr = hsotg->regs + GNPTXFSIZ;
|
|
dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
|
|
addr = hsotg->regs + GNPTXSTS;
|
|
dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
|
|
addr = hsotg->regs + GI2CCTL;
|
|
dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
|
|
addr = hsotg->regs + GPVNDCTL;
|
|
dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
|
|
addr = hsotg->regs + GGPIO;
|
|
dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GGPIO));
|
|
addr = hsotg->regs + GUID;
|
|
dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GUID));
|
|
addr = hsotg->regs + GSNPSID;
|
|
dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
|
|
addr = hsotg->regs + GHWCFG1;
|
|
dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
|
|
addr = hsotg->regs + GHWCFG2;
|
|
dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
|
|
addr = hsotg->regs + GHWCFG3;
|
|
dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
|
|
addr = hsotg->regs + GHWCFG4;
|
|
dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
|
|
addr = hsotg->regs + GLPMCFG;
|
|
dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
|
|
addr = hsotg->regs + GPWRDN;
|
|
dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
|
|
addr = hsotg->regs + GDFIFOCFG;
|
|
dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
|
|
addr = hsotg->regs + HPTXFSIZ;
|
|
dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
|
|
|
|
addr = hsotg->regs + PCGCTL;
|
|
dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
|
|
(unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* dwc2_flush_tx_fifo() - Flushes a Tx FIFO
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
* @num: Tx FIFO to flush
|
|
*/
|
|
void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
|
|
{
|
|
u32 greset;
|
|
|
|
dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
|
|
|
|
/* Wait for AHB master IDLE state */
|
|
if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
|
|
dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
|
|
__func__);
|
|
|
|
greset = GRSTCTL_TXFFLSH;
|
|
greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
|
|
dwc2_writel(hsotg, greset, GRSTCTL);
|
|
|
|
if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
|
|
dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
|
|
__func__);
|
|
|
|
/* Wait for at least 3 PHY Clocks */
|
|
udelay(1);
|
|
}
|
|
|
|
/**
|
|
* dwc2_flush_rx_fifo() - Flushes the Rx FIFO
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 greset;
|
|
|
|
dev_vdbg(hsotg->dev, "%s()\n", __func__);
|
|
|
|
/* Wait for AHB master IDLE state */
|
|
if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
|
|
dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
|
|
__func__);
|
|
|
|
greset = GRSTCTL_RXFFLSH;
|
|
dwc2_writel(hsotg, greset, GRSTCTL);
|
|
|
|
/* Wait for RxFIFO flush done */
|
|
if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
|
|
dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
|
|
__func__);
|
|
|
|
/* Wait for at least 3 PHY Clocks */
|
|
udelay(1);
|
|
}
|
|
|
|
bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
|
|
{
|
|
if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
|
|
return false;
|
|
else
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* dwc2_enable_global_interrupts() - Enables the controller's Global
|
|
* Interrupt in the AHB Config register
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
|
|
|
|
ahbcfg |= GAHBCFG_GLBL_INTR_EN;
|
|
dwc2_writel(hsotg, ahbcfg, GAHBCFG);
|
|
}
|
|
|
|
/**
|
|
* dwc2_disable_global_interrupts() - Disables the controller's Global
|
|
* Interrupt in the AHB Config register
|
|
*
|
|
* @hsotg: Programming view of DWC_otg controller
|
|
*/
|
|
void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
|
|
|
|
ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
|
|
dwc2_writel(hsotg, ahbcfg, GAHBCFG);
|
|
}
|
|
|
|
/* Returns the controller's GHWCFG2.OTG_MODE. */
|
|
unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
|
|
{
|
|
u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
|
|
|
|
return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
|
|
GHWCFG2_OP_MODE_SHIFT;
|
|
}
|
|
|
|
/* Returns true if the controller is capable of DRD. */
|
|
bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned int op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
|
|
}
|
|
|
|
/* Returns true if the controller is host-only. */
|
|
bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned int op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
|
|
}
|
|
|
|
/* Returns true if the controller is device-only. */
|
|
bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
|
|
{
|
|
unsigned int op_mode = dwc2_op_mode(hsotg);
|
|
|
|
return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
|
|
(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
|
|
}
|
|
|
|
/**
|
|
* dwc2_hsotg_wait_bit_set - Waits for bit to be set.
|
|
* @hsotg: Programming view of DWC_otg controller.
|
|
* @offset: Register's offset where bit/bits must be set.
|
|
* @mask: Mask of the bit/bits which must be set.
|
|
* @timeout: Timeout to wait.
|
|
*
|
|
* Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
|
|
*/
|
|
int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
|
|
u32 timeout)
|
|
{
|
|
u32 i;
|
|
|
|
for (i = 0; i < timeout; i++) {
|
|
if (dwc2_readl(hsotg, offset) & mask)
|
|
return 0;
|
|
udelay(1);
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
/**
|
|
* dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
|
|
* @hsotg: Programming view of DWC_otg controller.
|
|
* @offset: Register's offset where bit/bits must be set.
|
|
* @mask: Mask of the bit/bits which must be set.
|
|
* @timeout: Timeout to wait.
|
|
*
|
|
* Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
|
|
*/
|
|
int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
|
|
u32 timeout)
|
|
{
|
|
u32 i;
|
|
|
|
for (i = 0; i < timeout; i++) {
|
|
if (!(dwc2_readl(hsotg, offset) & mask))
|
|
return 0;
|
|
udelay(1);
|
|
}
|
|
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
|
|
MODULE_AUTHOR("Synopsys, Inc.");
|
|
MODULE_LICENSE("Dual BSD/GPL");
|