linux_old1/arch/arm/mach-mmp
Tony Lindgren 4e6d488af3 ARM: 5910/1: ARM: Add tmp register for addruart and loadsp
Otherwise more complicated uart configuration won't be possible.
We can use r1 for tmp register for both head.S and debug.S.

NOTE: This patch depends on another patch to add the the tmp register
into all debug-macro.S files. That can be done with:

$ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/"
	arch/arm/*/include/*/debug-macro.S

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-12 17:27:52 +00:00
..
include/mach ARM: 5910/1: ARM: Add tmp register for addruart and loadsp 2010-02-12 17:27:52 +00:00
Kconfig [ARM] pxa: add base support for pxa910-based TTC_DKB 2009-03-23 10:11:38 +08:00
Makefile [ARM] pxa: add base support for pxa910-based TTC_DKB 2009-03-23 10:11:38 +08:00
Makefile.boot [ARM] pxa: add base support for Marvell's PXA168 processor line 2009-03-23 10:11:34 +08:00
aspenite.c [ARM] pxa: add nand support in aspensite board 2009-12-01 09:02:44 +08:00
clock.c [ARM] pxa: add apmu clock support in mmp 2009-12-01 09:02:51 +08:00
clock.h [ARM] pxa: add apmu clock support in mmp 2009-12-01 09:02:51 +08:00
common.c [ARM] pxa: add base support for Marvell's PXA168 processor line 2009-03-23 10:11:34 +08:00
common.h [ARM] pxa: add base support for Marvell PXA910 2009-03-23 10:11:35 +08:00
devices.c [ARM] pxa: add base support for Marvell's PXA168 processor line 2009-03-23 10:11:34 +08:00
irq.c [ARM] pxa: add base support for Marvell's PXA168 processor line 2009-03-23 10:11:34 +08:00
pxa168.c [ARM] pxa: add nand device and clock for pxa168/pxa910 2009-12-01 09:02:43 +08:00
pxa910.c [ARM] pxa: add nand device and clock for pxa168/pxa910 2009-12-01 09:02:43 +08:00
tavorevb.c [ARM] pxa: add base support for pxa910-based TavorEVB 2009-03-23 10:11:38 +08:00
time.c [ARM] pxa: add parameter to clksrc_read() for pxa168/910 2009-05-22 18:15:49 +08:00
ttc_dkb.c [ARM] pxa/ttc_dkb: remove duplicate macro definition 2009-12-29 14:11:33 +08:00