366 lines
8.1 KiB
ArmAsm
366 lines
8.1 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
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*
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* Multi-arch abstraction and asm macros for easier reading:
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/errno.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
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#undef fp
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.macro EX insn, reg, src
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.set push
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SET_HARDFLOAT
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.set nomacro
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.ex\@: \insn \reg, \src
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.set pop
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.section __ex_table,"a"
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PTR .ex\@, fault
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.previous
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.endm
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.set noreorder
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/**
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* _save_fp_context() - save FP context from the FPU
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* @a0 - pointer to fpregs field of sigcontext
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* @a1 - pointer to fpc_csr field of sigcontext
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*
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* Save FP context, including the 32 FP data registers and the FP
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* control & status register, from the FPU to signal context.
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*/
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LEAF(_save_fp_context)
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.set push
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SET_HARDFLOAT
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cfc1 t1, fcr31
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.set pop
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
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defined(CONFIG_CPU_MIPS32_R6)
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.set push
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SET_HARDFLOAT
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#ifdef CONFIG_CPU_MIPS32_R2
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.set mips32r2
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.set fp=64
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mfc0 t0, CP0_STATUS
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sll t0, t0, 5
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bgez t0, 1f # skip storing odd if FR=0
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nop
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#endif
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/* Store the 16 odd double precision registers */
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EX sdc1 $f1, 8(a0)
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EX sdc1 $f3, 24(a0)
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EX sdc1 $f5, 40(a0)
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EX sdc1 $f7, 56(a0)
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EX sdc1 $f9, 72(a0)
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EX sdc1 $f11, 88(a0)
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EX sdc1 $f13, 104(a0)
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EX sdc1 $f15, 120(a0)
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EX sdc1 $f17, 136(a0)
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EX sdc1 $f19, 152(a0)
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EX sdc1 $f21, 168(a0)
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EX sdc1 $f23, 184(a0)
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EX sdc1 $f25, 200(a0)
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EX sdc1 $f27, 216(a0)
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EX sdc1 $f29, 232(a0)
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EX sdc1 $f31, 248(a0)
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1: .set pop
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#endif
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.set push
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SET_HARDFLOAT
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/* Store the 16 even double precision registers */
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EX sdc1 $f0, 0(a0)
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EX sdc1 $f2, 16(a0)
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EX sdc1 $f4, 32(a0)
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EX sdc1 $f6, 48(a0)
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EX sdc1 $f8, 64(a0)
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EX sdc1 $f10, 80(a0)
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EX sdc1 $f12, 96(a0)
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EX sdc1 $f14, 112(a0)
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EX sdc1 $f16, 128(a0)
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EX sdc1 $f18, 144(a0)
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EX sdc1 $f20, 160(a0)
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EX sdc1 $f22, 176(a0)
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EX sdc1 $f24, 192(a0)
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EX sdc1 $f26, 208(a0)
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EX sdc1 $f28, 224(a0)
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EX sdc1 $f30, 240(a0)
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EX sw t1, 0(a1)
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jr ra
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li v0, 0 # success
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.set pop
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END(_save_fp_context)
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/**
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* _restore_fp_context() - restore FP context to the FPU
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* @a0 - pointer to fpregs field of sigcontext
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* @a1 - pointer to fpc_csr field of sigcontext
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*
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* Restore FP context, including the 32 FP data registers and the FP
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* control & status register, from signal context to the FPU.
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*/
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LEAF(_restore_fp_context)
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EX lw t1, 0(a1)
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
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defined(CONFIG_CPU_MIPS32_R6)
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.set push
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SET_HARDFLOAT
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#ifdef CONFIG_CPU_MIPS32_R2
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.set mips32r2
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.set fp=64
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mfc0 t0, CP0_STATUS
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sll t0, t0, 5
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bgez t0, 1f # skip loading odd if FR=0
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nop
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#endif
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EX ldc1 $f1, 8(a0)
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EX ldc1 $f3, 24(a0)
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EX ldc1 $f5, 40(a0)
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EX ldc1 $f7, 56(a0)
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EX ldc1 $f9, 72(a0)
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EX ldc1 $f11, 88(a0)
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EX ldc1 $f13, 104(a0)
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EX ldc1 $f15, 120(a0)
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EX ldc1 $f17, 136(a0)
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EX ldc1 $f19, 152(a0)
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EX ldc1 $f21, 168(a0)
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EX ldc1 $f23, 184(a0)
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EX ldc1 $f25, 200(a0)
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EX ldc1 $f27, 216(a0)
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EX ldc1 $f29, 232(a0)
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EX ldc1 $f31, 248(a0)
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1: .set pop
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#endif
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.set push
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SET_HARDFLOAT
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EX ldc1 $f0, 0(a0)
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EX ldc1 $f2, 16(a0)
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EX ldc1 $f4, 32(a0)
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EX ldc1 $f6, 48(a0)
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EX ldc1 $f8, 64(a0)
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EX ldc1 $f10, 80(a0)
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EX ldc1 $f12, 96(a0)
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EX ldc1 $f14, 112(a0)
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EX ldc1 $f16, 128(a0)
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EX ldc1 $f18, 144(a0)
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EX ldc1 $f20, 160(a0)
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EX ldc1 $f22, 176(a0)
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EX ldc1 $f24, 192(a0)
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EX ldc1 $f26, 208(a0)
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EX ldc1 $f28, 224(a0)
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EX ldc1 $f30, 240(a0)
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ctc1 t1, fcr31
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.set pop
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jr ra
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li v0, 0 # success
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END(_restore_fp_context)
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#ifdef CONFIG_CPU_HAS_MSA
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.macro op_one_wr op, idx, base
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.align 4
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\idx: \op \idx, 0, \base
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jr ra
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nop
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.endm
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.macro op_msa_wr name, op
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LEAF(\name)
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.set push
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.set noreorder
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sll t0, a0, 4
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PTR_LA t1, 0f
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PTR_ADDU t0, t0, t1
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jr t0
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nop
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op_one_wr \op, 0, a1
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op_one_wr \op, 1, a1
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op_one_wr \op, 2, a1
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op_one_wr \op, 3, a1
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op_one_wr \op, 4, a1
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op_one_wr \op, 5, a1
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op_one_wr \op, 6, a1
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op_one_wr \op, 7, a1
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op_one_wr \op, 8, a1
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op_one_wr \op, 9, a1
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op_one_wr \op, 10, a1
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op_one_wr \op, 11, a1
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op_one_wr \op, 12, a1
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op_one_wr \op, 13, a1
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op_one_wr \op, 14, a1
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op_one_wr \op, 15, a1
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op_one_wr \op, 16, a1
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op_one_wr \op, 17, a1
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op_one_wr \op, 18, a1
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op_one_wr \op, 19, a1
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op_one_wr \op, 20, a1
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op_one_wr \op, 21, a1
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op_one_wr \op, 22, a1
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op_one_wr \op, 23, a1
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op_one_wr \op, 24, a1
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op_one_wr \op, 25, a1
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op_one_wr \op, 26, a1
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op_one_wr \op, 27, a1
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op_one_wr \op, 28, a1
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op_one_wr \op, 29, a1
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op_one_wr \op, 30, a1
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op_one_wr \op, 31, a1
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.set pop
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END(\name)
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.endm
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op_msa_wr read_msa_wr_b, st_b
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op_msa_wr read_msa_wr_h, st_h
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op_msa_wr read_msa_wr_w, st_w
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op_msa_wr read_msa_wr_d, st_d
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op_msa_wr write_msa_wr_b, ld_b
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op_msa_wr write_msa_wr_h, ld_h
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op_msa_wr write_msa_wr_w, ld_w
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op_msa_wr write_msa_wr_d, ld_d
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#endif /* CONFIG_CPU_HAS_MSA */
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#ifdef CONFIG_CPU_HAS_MSA
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.macro save_msa_upper wr, off, base
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.set push
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.set noat
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#ifdef CONFIG_64BIT
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copy_u_d \wr, 1
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EX sd $1, \off(\base)
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#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
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copy_u_w \wr, 2
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EX sw $1, \off(\base)
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copy_u_w \wr, 3
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EX sw $1, (\off+4)(\base)
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#else /* CONFIG_CPU_BIG_ENDIAN */
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copy_u_w \wr, 2
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EX sw $1, (\off+4)(\base)
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copy_u_w \wr, 3
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EX sw $1, \off(\base)
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#endif
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.set pop
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.endm
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LEAF(_save_msa_all_upper)
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save_msa_upper 0, 0x00, a0
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save_msa_upper 1, 0x08, a0
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save_msa_upper 2, 0x10, a0
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save_msa_upper 3, 0x18, a0
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save_msa_upper 4, 0x20, a0
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save_msa_upper 5, 0x28, a0
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save_msa_upper 6, 0x30, a0
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save_msa_upper 7, 0x38, a0
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save_msa_upper 8, 0x40, a0
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save_msa_upper 9, 0x48, a0
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save_msa_upper 10, 0x50, a0
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save_msa_upper 11, 0x58, a0
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save_msa_upper 12, 0x60, a0
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save_msa_upper 13, 0x68, a0
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save_msa_upper 14, 0x70, a0
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save_msa_upper 15, 0x78, a0
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save_msa_upper 16, 0x80, a0
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save_msa_upper 17, 0x88, a0
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save_msa_upper 18, 0x90, a0
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save_msa_upper 19, 0x98, a0
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save_msa_upper 20, 0xa0, a0
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save_msa_upper 21, 0xa8, a0
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save_msa_upper 22, 0xb0, a0
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save_msa_upper 23, 0xb8, a0
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save_msa_upper 24, 0xc0, a0
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save_msa_upper 25, 0xc8, a0
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save_msa_upper 26, 0xd0, a0
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save_msa_upper 27, 0xd8, a0
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save_msa_upper 28, 0xe0, a0
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save_msa_upper 29, 0xe8, a0
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save_msa_upper 30, 0xf0, a0
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save_msa_upper 31, 0xf8, a0
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jr ra
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li v0, 0
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END(_save_msa_all_upper)
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.macro restore_msa_upper wr, off, base
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.set push
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.set noat
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#ifdef CONFIG_64BIT
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EX ld $1, \off(\base)
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insert_d \wr, 1
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#elif defined(CONFIG_CPU_LITTLE_ENDIAN)
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EX lw $1, \off(\base)
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insert_w \wr, 2
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EX lw $1, (\off+4)(\base)
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insert_w \wr, 3
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#else /* CONFIG_CPU_BIG_ENDIAN */
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EX lw $1, (\off+4)(\base)
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insert_w \wr, 2
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EX lw $1, \off(\base)
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insert_w \wr, 3
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#endif
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.set pop
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.endm
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LEAF(_restore_msa_all_upper)
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restore_msa_upper 0, 0x00, a0
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restore_msa_upper 1, 0x08, a0
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restore_msa_upper 2, 0x10, a0
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restore_msa_upper 3, 0x18, a0
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restore_msa_upper 4, 0x20, a0
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restore_msa_upper 5, 0x28, a0
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restore_msa_upper 6, 0x30, a0
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restore_msa_upper 7, 0x38, a0
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restore_msa_upper 8, 0x40, a0
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restore_msa_upper 9, 0x48, a0
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restore_msa_upper 10, 0x50, a0
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restore_msa_upper 11, 0x58, a0
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restore_msa_upper 12, 0x60, a0
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restore_msa_upper 13, 0x68, a0
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restore_msa_upper 14, 0x70, a0
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restore_msa_upper 15, 0x78, a0
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restore_msa_upper 16, 0x80, a0
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restore_msa_upper 17, 0x88, a0
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restore_msa_upper 18, 0x90, a0
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restore_msa_upper 19, 0x98, a0
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restore_msa_upper 20, 0xa0, a0
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restore_msa_upper 21, 0xa8, a0
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restore_msa_upper 22, 0xb0, a0
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restore_msa_upper 23, 0xb8, a0
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restore_msa_upper 24, 0xc0, a0
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restore_msa_upper 25, 0xc8, a0
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restore_msa_upper 26, 0xd0, a0
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restore_msa_upper 27, 0xd8, a0
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restore_msa_upper 28, 0xe0, a0
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restore_msa_upper 29, 0xe8, a0
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restore_msa_upper 30, 0xf0, a0
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restore_msa_upper 31, 0xf8, a0
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jr ra
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li v0, 0
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END(_restore_msa_all_upper)
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#endif /* CONFIG_CPU_HAS_MSA */
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.set reorder
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.type fault@function
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.ent fault
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fault: li v0, -EFAULT # failure
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jr ra
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.end fault
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