320 lines
7.5 KiB
C
320 lines
7.5 KiB
C
/*
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* KVM PMU support for AMD
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*
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* Copyright 2015, Red Hat, Inc. and/or its affiliates.
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*
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* Author:
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* Wei Huang <wei@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* Implementation is based on pmu_intel.c file
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*/
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include "x86.h"
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#include "cpuid.h"
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#include "lapic.h"
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#include "pmu.h"
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enum pmu_type {
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PMU_TYPE_COUNTER = 0,
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PMU_TYPE_EVNTSEL,
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};
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enum index {
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INDEX_ZERO = 0,
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INDEX_ONE,
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INDEX_TWO,
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INDEX_THREE,
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INDEX_FOUR,
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INDEX_FIVE,
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INDEX_ERROR,
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};
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/* duplicated from amd_perfmon_event_map, K7 and above should work. */
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static struct kvm_event_hw_type_mapping amd_event_mapping[] = {
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[0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES },
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[1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
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[2] = { 0x7d, 0x07, PERF_COUNT_HW_CACHE_REFERENCES },
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[3] = { 0x7e, 0x07, PERF_COUNT_HW_CACHE_MISSES },
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[4] = { 0xc2, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
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[5] = { 0xc3, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
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[6] = { 0xd0, 0x00, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND },
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[7] = { 0xd1, 0x00, PERF_COUNT_HW_STALLED_CYCLES_BACKEND },
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};
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static unsigned int get_msr_base(struct kvm_pmu *pmu, enum pmu_type type)
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{
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struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
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if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
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if (type == PMU_TYPE_COUNTER)
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return MSR_F15H_PERF_CTR;
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else
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return MSR_F15H_PERF_CTL;
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} else {
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if (type == PMU_TYPE_COUNTER)
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return MSR_K7_PERFCTR0;
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else
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return MSR_K7_EVNTSEL0;
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}
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}
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static enum index msr_to_index(u32 msr)
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{
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switch (msr) {
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case MSR_F15H_PERF_CTL0:
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case MSR_F15H_PERF_CTR0:
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case MSR_K7_EVNTSEL0:
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case MSR_K7_PERFCTR0:
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return INDEX_ZERO;
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case MSR_F15H_PERF_CTL1:
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case MSR_F15H_PERF_CTR1:
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case MSR_K7_EVNTSEL1:
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case MSR_K7_PERFCTR1:
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return INDEX_ONE;
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case MSR_F15H_PERF_CTL2:
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case MSR_F15H_PERF_CTR2:
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case MSR_K7_EVNTSEL2:
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case MSR_K7_PERFCTR2:
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return INDEX_TWO;
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case MSR_F15H_PERF_CTL3:
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case MSR_F15H_PERF_CTR3:
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case MSR_K7_EVNTSEL3:
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case MSR_K7_PERFCTR3:
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return INDEX_THREE;
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case MSR_F15H_PERF_CTL4:
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case MSR_F15H_PERF_CTR4:
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return INDEX_FOUR;
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case MSR_F15H_PERF_CTL5:
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case MSR_F15H_PERF_CTR5:
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return INDEX_FIVE;
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default:
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return INDEX_ERROR;
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}
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}
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static inline struct kvm_pmc *get_gp_pmc_amd(struct kvm_pmu *pmu, u32 msr,
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enum pmu_type type)
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{
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switch (msr) {
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case MSR_F15H_PERF_CTL0:
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case MSR_F15H_PERF_CTL1:
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case MSR_F15H_PERF_CTL2:
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case MSR_F15H_PERF_CTL3:
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case MSR_F15H_PERF_CTL4:
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case MSR_F15H_PERF_CTL5:
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case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
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if (type != PMU_TYPE_EVNTSEL)
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return NULL;
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break;
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case MSR_F15H_PERF_CTR0:
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case MSR_F15H_PERF_CTR1:
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case MSR_F15H_PERF_CTR2:
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case MSR_F15H_PERF_CTR3:
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case MSR_F15H_PERF_CTR4:
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case MSR_F15H_PERF_CTR5:
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case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
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if (type != PMU_TYPE_COUNTER)
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return NULL;
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break;
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default:
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return NULL;
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}
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return &pmu->gp_counters[msr_to_index(msr)];
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}
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static unsigned amd_find_arch_event(struct kvm_pmu *pmu,
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u8 event_select,
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u8 unit_mask)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(amd_event_mapping); i++)
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if (amd_event_mapping[i].eventsel == event_select
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&& amd_event_mapping[i].unit_mask == unit_mask)
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break;
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if (i == ARRAY_SIZE(amd_event_mapping))
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return PERF_COUNT_HW_MAX;
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return amd_event_mapping[i].event_type;
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}
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/* return PERF_COUNT_HW_MAX as AMD doesn't have fixed events */
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static unsigned amd_find_fixed_event(int idx)
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{
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return PERF_COUNT_HW_MAX;
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}
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/* check if a PMC is enabled by comparing it against global_ctrl bits. Because
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* AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE).
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*/
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static bool amd_pmc_is_enabled(struct kvm_pmc *pmc)
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{
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return true;
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}
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static struct kvm_pmc *amd_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
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{
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unsigned int base = get_msr_base(pmu, PMU_TYPE_COUNTER);
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struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
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if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) {
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/*
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* The idx is contiguous. The MSRs are not. The counter MSRs
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* are interleaved with the event select MSRs.
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*/
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pmc_idx *= 2;
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}
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return get_gp_pmc_amd(pmu, base + pmc_idx, PMU_TYPE_COUNTER);
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}
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/* returns 0 if idx's corresponding MSR exists; otherwise returns 1. */
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static int amd_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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idx &= ~(3u << 30);
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return (idx >= pmu->nr_arch_gp_counters);
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}
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/* idx is the ECX register of RDPMC instruction */
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static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, unsigned idx)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *counters;
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idx &= ~(3u << 30);
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if (idx >= pmu->nr_arch_gp_counters)
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return NULL;
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counters = pmu->gp_counters;
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return &counters[idx];
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}
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static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int ret = false;
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ret = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER) ||
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get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
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return ret;
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}
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static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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/* MSR_PERFCTRn */
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pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
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if (pmc) {
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*data = pmc_read_counter(pmc);
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return 0;
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}
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/* MSR_EVNTSELn */
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pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
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if (pmc) {
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*data = pmc->eventsel;
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return 0;
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}
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return 1;
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}
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static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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struct kvm_pmc *pmc;
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u32 msr = msr_info->index;
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u64 data = msr_info->data;
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/* MSR_PERFCTRn */
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pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_COUNTER);
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if (pmc) {
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pmc->counter += data - pmc_read_counter(pmc);
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return 0;
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}
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/* MSR_EVNTSELn */
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pmc = get_gp_pmc_amd(pmu, msr, PMU_TYPE_EVNTSEL);
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if (pmc) {
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if (data == pmc->eventsel)
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return 0;
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if (!(data & pmu->reserved_bits)) {
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reprogram_gp_counter(pmc, data);
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return 0;
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}
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}
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return 1;
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}
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static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE))
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pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE;
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else
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pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS;
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pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
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pmu->reserved_bits = 0xffffffff00200000ull;
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/* not applicable to AMD; but clean them to prevent any fall out */
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pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
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pmu->nr_arch_fixed_counters = 0;
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pmu->version = 0;
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pmu->global_status = 0;
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}
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static void amd_pmu_init(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int i;
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BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > INTEL_PMC_MAX_GENERIC);
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for (i = 0; i < AMD64_NUM_COUNTERS_CORE ; i++) {
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pmu->gp_counters[i].type = KVM_PMC_GP;
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pmu->gp_counters[i].vcpu = vcpu;
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pmu->gp_counters[i].idx = i;
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}
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}
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static void amd_pmu_reset(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int i;
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for (i = 0; i < AMD64_NUM_COUNTERS_CORE; i++) {
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struct kvm_pmc *pmc = &pmu->gp_counters[i];
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pmc_stop_counter(pmc);
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pmc->counter = pmc->eventsel = 0;
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}
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}
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struct kvm_pmu_ops amd_pmu_ops = {
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.find_arch_event = amd_find_arch_event,
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.find_fixed_event = amd_find_fixed_event,
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.pmc_is_enabled = amd_pmc_is_enabled,
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.pmc_idx_to_pmc = amd_pmc_idx_to_pmc,
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.msr_idx_to_pmc = amd_msr_idx_to_pmc,
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.is_valid_msr_idx = amd_is_valid_msr_idx,
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.is_valid_msr = amd_is_valid_msr,
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.get_msr = amd_pmu_get_msr,
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.set_msr = amd_pmu_set_msr,
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.refresh = amd_pmu_refresh,
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.init = amd_pmu_init,
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.reset = amd_pmu_reset,
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};
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