145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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static struct drm_mm_node *
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nv20_fb_alloc_tag(struct drm_device *dev, uint32_t size)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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struct drm_mm_node *mem;
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int ret;
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ret = drm_mm_pre_get(&pfb->tag_heap);
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if (ret)
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return NULL;
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spin_lock(&dev_priv->tile.lock);
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mem = drm_mm_search_free(&pfb->tag_heap, size, 0, 0);
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if (mem)
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mem = drm_mm_get_block_atomic(mem, size, 0);
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spin_unlock(&dev_priv->tile.lock);
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return mem;
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}
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static void
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nv20_fb_free_tag(struct drm_device *dev, struct drm_mm_node *mem)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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spin_lock(&dev_priv->tile.lock);
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drm_mm_put_block(mem);
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spin_unlock(&dev_priv->tile.lock);
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}
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void
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nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch, uint32_t flags)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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int bpp = (flags & NOUVEAU_GEM_TILE_32BPP ? 32 : 16);
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tile->addr = addr;
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tile->limit = max(1u, addr + size) - 1;
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tile->pitch = pitch;
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if (dev_priv->card_type == NV_20) {
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if (flags & NOUVEAU_GEM_TILE_ZETA) {
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/*
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* Allocate some of the on-die tag memory,
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* used to store Z compression meta-data (most
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* likely just a bitmap determining if a given
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* tile is compressed or not).
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*/
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tile->tag_mem = nv20_fb_alloc_tag(dev, size / 256);
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if (tile->tag_mem) {
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/* Enable Z compression */
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if (dev_priv->chipset >= 0x25)
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tile->zcomp = tile->tag_mem->start |
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(bpp == 16 ?
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NV25_PFB_ZCOMP_MODE_16 :
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NV25_PFB_ZCOMP_MODE_32);
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else
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tile->zcomp = tile->tag_mem->start |
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NV20_PFB_ZCOMP_EN |
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(bpp == 16 ? 0 :
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NV20_PFB_ZCOMP_MODE_32);
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}
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tile->addr |= 3;
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} else {
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tile->addr |= 1;
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}
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} else {
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tile->addr |= 1 << 31;
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}
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}
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void
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nv10_fb_free_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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if (tile->tag_mem) {
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nv20_fb_free_tag(dev, tile->tag_mem);
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tile->tag_mem = NULL;
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}
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tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
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}
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void
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nv10_fb_set_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
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nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
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nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
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if (dev_priv->card_type == NV_20)
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nv_wr32(dev, NV20_PFB_ZCOMP(i), tile->zcomp);
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}
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int
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nv10_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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int i;
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pfb->num_tiles = NV10_PFB_TILE__SIZE;
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if (dev_priv->card_type == NV_20)
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drm_mm_init(&pfb->tag_heap, 0,
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(dev_priv->chipset >= 0x25 ?
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64 * 1024 : 32 * 1024));
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/* Turn all the tiling regions off. */
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for (i = 0; i < pfb->num_tiles; i++)
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pfb->set_tile_region(dev, i);
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return 0;
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}
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void
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nv10_fb_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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int i;
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for (i = 0; i < pfb->num_tiles; i++)
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pfb->free_tile_region(dev, i);
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if (dev_priv->card_type == NV_20)
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drm_mm_takedown(&pfb->tag_heap);
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}
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