255 lines
6.0 KiB
C
255 lines
6.0 KiB
C
/* linux/arch/arm/mach-exynos4/cpu.c
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/sysdev.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/proc-fns.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/hardware/gic.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/exynos4.h>
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#include <plat/adc-core.h>
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#include <plat/sdhci.h>
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#include <plat/fb-core.h>
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#include <plat/fimc-core.h>
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#include <plat/iic-core.h>
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#include <plat/reset.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-pmu.h>
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extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
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unsigned int irq_start);
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extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
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/* Initial IO mappings */
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_SYSTIMER,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SYSRAM,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_CMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
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.length = SZ_128K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_PMU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
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.length = SZ_8K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_L2CC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GPIO1,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GPIO2,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GPIO3,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
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.length = SZ_256,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_DMC0,
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.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_UART,
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.length = SZ_512K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_USB_HSPHY,
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.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_CPU,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
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.length = SZ_64K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S5P_VA_GIC_DIST,
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.pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
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.length = SZ_64K,
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.type = MT_DEVICE,
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},
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};
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static void exynos4_idle(void)
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{
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if (!need_resched())
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cpu_do_idle();
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local_irq_enable();
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}
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static void exynos4_sw_reset(void)
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{
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__raw_writel(0x1, S5P_SWRESET);
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}
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/*
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* exynos4_map_io
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*
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* register the standard cpu IO areas
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*/
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void __init exynos4_map_io(void)
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{
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iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
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/* initialize device information early */
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exynos4_default_sdhci0();
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exynos4_default_sdhci1();
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exynos4_default_sdhci2();
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exynos4_default_sdhci3();
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s3c_adc_setname("samsung-adc-v3");
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s3c_fimc_setname(0, "exynos4-fimc");
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s3c_fimc_setname(1, "exynos4-fimc");
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s3c_fimc_setname(2, "exynos4-fimc");
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s3c_fimc_setname(3, "exynos4-fimc");
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/* The I2C bus controllers are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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s3c_i2c1_setname("s3c2440-i2c");
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s3c_i2c2_setname("s3c2440-i2c");
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s5p_fb_setname(0, "exynos4-fb");
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}
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void __init exynos4_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
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s3c24xx_register_baseclocks(xtal);
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s5p_register_clocks(xtal);
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exynos4_register_clocks();
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exynos4_setup_clocks();
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}
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static void exynos4_gic_irq_eoi(struct irq_data *d)
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{
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struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
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gic_data->cpu_base = S5P_VA_GIC_CPU +
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(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
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}
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void __init exynos4_init_irq(void)
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{
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int irq;
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gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
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gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
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for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
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combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
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COMBINER_IRQ(irq, 0));
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combiner_cascade_irq(irq, IRQ_SPI(irq));
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}
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/* The parameters of s5p_init_irq() are for VIC init.
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* Theses parameters should be NULL and 0 because EXYNOS4
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* uses GIC instead of VIC.
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*/
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s5p_init_irq(NULL, 0);
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}
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struct sysdev_class exynos4_sysclass = {
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.name = "exynos4-core",
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};
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static struct sys_device exynos4_sysdev = {
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.cls = &exynos4_sysclass,
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};
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static int __init exynos4_core_init(void)
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{
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return sysdev_class_register(&exynos4_sysclass);
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}
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core_initcall(exynos4_core_init);
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#ifdef CONFIG_CACHE_L2X0
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static int __init exynos4_l2x0_cache_init(void)
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{
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/* TAG, Data Latency Control: 2cycle */
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__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
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__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
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/* L2X0 Prefetch Control */
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__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
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/* L2X0 Power Control */
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__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
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S5P_VA_L2CC + L2X0_POWER_CTRL);
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l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
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return 0;
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}
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early_initcall(exynos4_l2x0_cache_init);
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#endif
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int __init exynos4_init(void)
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{
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printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
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/* set idle function */
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pm_idle = exynos4_idle;
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/* set sw_reset function */
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s5p_reset_hook = exynos4_sw_reset;
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return sysdev_register(&exynos4_sysdev);
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}
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