468 lines
12 KiB
C
468 lines
12 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_ap.c
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*
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/syscore_ops.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mtd/physmap.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/param.h> /* HZ */
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#include <asm/mach-types.h>
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#include <mach/lm.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <plat/fpga-irq.h>
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#include "common.h"
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/*
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* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
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* is the (PA >> 12).
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*
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* Setup a VA for the Integrator interrupt controller (for header #0,
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* just for now).
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*/
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#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
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#define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
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#define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
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#define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
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/*
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* Logical Physical
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* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
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* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
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* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
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* ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
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* ef000000 Cache flush
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* f1000000 10000000 Core module registers
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* f1100000 11000000 System controller registers
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* f1200000 12000000 EBI registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* f1b00000 1b000000 GPIO
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*/
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static struct map_desc ap_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_MEMORY_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_CONFIG_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
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.length = SZ_16M,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_V3_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
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.length = SZ_64K,
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.type = MT_DEVICE
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}, {
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.virtual = PCI_IO_VADDR,
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.pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
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.length = SZ_64K,
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.type = MT_DEVICE
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}
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};
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static void __init ap_map_io(void)
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{
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iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
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}
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#define INTEGRATOR_SC_VALID_INT 0x003fffff
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static struct fpga_irq_data sc_irq_data = {
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.base = VA_IC_BASE,
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.irq_start = 0,
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.chip.name = "SC",
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};
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static void __init ap_init_irq(void)
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{
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/* Disable all interrupts initially. */
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/* Do the core module ones */
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writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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/* do the header card stuff next */
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
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}
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#ifdef CONFIG_PM
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static unsigned long ic_irq_enable;
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static int irq_suspend(void)
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{
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ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
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return 0;
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}
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static void irq_resume(void)
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{
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/* disable all irq sources */
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writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
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}
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#else
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#define irq_suspend NULL
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#define irq_resume NULL
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#endif
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static struct syscore_ops irq_syscore_ops = {
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.suspend = irq_suspend,
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.resume = irq_resume,
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};
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static int __init irq_syscore_init(void)
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{
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register_syscore_ops(&irq_syscore_ops);
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return 0;
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}
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device_initcall(irq_syscore_init);
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/*
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* Flash handling.
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*/
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#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
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#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
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#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
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#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
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static int ap_flash_init(struct platform_device *dev)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
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tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, EBI_CSR1);
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if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
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writel(0xa05f, EBI_LOCK);
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writel(tmp, EBI_CSR1);
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writel(0, EBI_LOCK);
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}
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return 0;
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}
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static void ap_flash_exit(struct platform_device *dev)
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{
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u32 tmp;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
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tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
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writel(tmp, EBI_CSR1);
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if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
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writel(0xa05f, EBI_LOCK);
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writel(tmp, EBI_CSR1);
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writel(0, EBI_LOCK);
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}
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}
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static void ap_flash_set_vpp(struct platform_device *pdev, int on)
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{
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void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
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writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
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}
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static struct physmap_flash_data ap_flash_data = {
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.width = 4,
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.init = ap_flash_init,
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.exit = ap_flash_exit,
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.set_vpp = ap_flash_set_vpp,
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};
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static struct resource cfi_flash_resource = {
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.start = INTEGRATOR_FLASH_BASE,
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.end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device cfi_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &ap_flash_data,
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},
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.num_resources = 1,
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.resource = &cfi_flash_resource,
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};
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static void __init ap_init(void)
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{
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unsigned long sc_dec;
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int i;
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platform_device_register(&cfi_flash_device);
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sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
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for (i = 0; i < 4; i++) {
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struct lm_device *lmdev;
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if ((sc_dec & (16 << i)) == 0)
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continue;
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lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
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if (!lmdev)
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continue;
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lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
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lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
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lmdev->resource.flags = IORESOURCE_MEM;
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lmdev->irq = IRQ_AP_EXPINT0 + i;
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lmdev->id = i;
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lm_device_register(lmdev);
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}
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}
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
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#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
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#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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static unsigned long timer_reload;
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static void integrator_clocksource_init(u32 khz)
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{
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void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
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u32 ctrl = TIMER_CTRL_ENABLE;
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if (khz >= 1500) {
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khz /= 16;
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ctrl = TIMER_CTRL_DIV16;
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}
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writel(ctrl, base + TIMER_CTRL);
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writel(0xffff, base + TIMER_LOAD);
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clocksource_mmio_init(base + TIMER_VALUE, "timer2",
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khz * 1000, 200, 16, clocksource_mmio_readl_down);
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}
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static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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writel(ctrl, clkevt_base + TIMER_CTRL);
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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}
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writel(ctrl, clkevt_base + TIMER_CTRL);
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.shift = 34,
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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.cpumask = cpu_all_mask,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(u32 khz)
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{
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struct clock_event_device *evt = &integrator_clockevent;
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unsigned int ctrl = 0;
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if (khz * 1000 > 0x100000 * HZ) {
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khz /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (khz * 1000 > 0x10000 * HZ) {
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khz /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = khz * 1000 / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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evt->irq = IRQ_TIMERINT1;
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evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
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evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
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setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
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clockevents_register_device(evt);
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}
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/*
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* Set up timer(s).
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*/
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static void __init ap_init_timer(void)
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{
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u32 khz = TICKS_PER_uSEC * 1000;
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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integrator_clocksource_init(khz);
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integrator_clockevent_init(khz);
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}
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static struct sys_timer ap_timer = {
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.init = ap_init_timer,
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};
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MACHINE_START(INTEGRATOR, "ARM-Integrator")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.boot_params = 0x00000100,
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.reserve = integrator_reserve,
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.map_io = ap_map_io,
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.init_early = integrator_init_early,
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.init_irq = ap_init_irq,
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.timer = &ap_timer,
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.init_machine = ap_init,
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MACHINE_END
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