217 lines
7.0 KiB
C
217 lines
7.0 KiB
C
/*****************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* Xilinx products are not intended for use in life support appliances,
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* devices, or systems. Use in such applications is expressly prohibited.
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*
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* (c) Copyright 2003-2007 Xilinx Inc.
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* All rights reserved.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*****************************************************************************/
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#ifndef XILINX_HWICAP_H_ /* prevent circular inclusions */
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#define XILINX_HWICAP_H_ /* by using protection macros */
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#include <linux/types.h>
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#include <linux/cdev.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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struct hwicap_drvdata {
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u32 write_buffer_in_use; /* Always in [0,3] */
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u8 write_buffer[4];
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u32 read_buffer_in_use; /* Always in [0,3] */
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u8 read_buffer[4];
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resource_size_t mem_start;/* phys. address of the control registers */
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resource_size_t mem_end; /* phys. address of the control registers */
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resource_size_t mem_size;
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void __iomem *base_address;/* virt. address of the control registers */
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struct device *dev;
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struct cdev cdev; /* Char device structure */
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dev_t devt;
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const struct hwicap_driver_config *config;
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const struct config_registers *config_regs;
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void *private_data;
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bool is_open;
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struct mutex sem;
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};
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struct hwicap_driver_config {
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/* Read configuration data given by size into the data buffer.
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Return 0 if successful. */
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int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
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u32 size);
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/* Write configuration data given by size from the data buffer.
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Return 0 if successful. */
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int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
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u32 size);
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/* Get the status register, bit pattern given by:
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* D8 - 0 = configuration error
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* D7 - 1 = alignment found
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* D6 - 1 = readback in progress
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* D5 - 0 = abort in progress
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* D4 - Always 1
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* D3 - Always 1
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* D2 - Always 1
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* D1 - Always 1
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* D0 - 1 = operation completed
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*/
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u32 (*get_status)(struct hwicap_drvdata *drvdata);
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/* Reset the hw */
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void (*reset)(struct hwicap_drvdata *drvdata);
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};
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/* Number of times to poll the done regsiter */
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#define XHI_MAX_RETRIES 10
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/************ Constant Definitions *************/
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#define XHI_PAD_FRAMES 0x1
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/* Mask for calculating configuration packet headers */
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#define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL
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#define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL
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#define XHI_TYPE_MASK 0x7
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#define XHI_REGISTER_MASK 0xF
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#define XHI_OP_MASK 0x3
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#define XHI_TYPE_SHIFT 29
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#define XHI_REGISTER_SHIFT 13
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#define XHI_OP_SHIFT 27
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#define XHI_TYPE_1 1
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#define XHI_TYPE_2 2
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#define XHI_OP_WRITE 2
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#define XHI_OP_READ 1
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/* Address Block Types */
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#define XHI_FAR_CLB_BLOCK 0
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#define XHI_FAR_BRAM_BLOCK 1
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#define XHI_FAR_BRAM_INT_BLOCK 2
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struct config_registers {
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u32 CRC;
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u32 FAR;
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u32 FDRI;
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u32 FDRO;
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u32 CMD;
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u32 CTL;
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u32 MASK;
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u32 STAT;
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u32 LOUT;
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u32 COR;
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u32 MFWR;
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u32 FLR;
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u32 KEY;
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u32 CBC;
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u32 IDCODE;
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u32 AXSS;
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u32 C0R_1;
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u32 CSOB;
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u32 WBSTAR;
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u32 TIMER;
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u32 BOOTSTS;
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u32 CTL_1;
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};
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/* Configuration Commands */
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#define XHI_CMD_NULL 0
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#define XHI_CMD_WCFG 1
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#define XHI_CMD_MFW 2
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#define XHI_CMD_DGHIGH 3
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#define XHI_CMD_RCFG 4
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#define XHI_CMD_START 5
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#define XHI_CMD_RCAP 6
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#define XHI_CMD_RCRC 7
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#define XHI_CMD_AGHIGH 8
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#define XHI_CMD_SWITCH 9
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#define XHI_CMD_GRESTORE 10
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#define XHI_CMD_SHUTDOWN 11
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#define XHI_CMD_GCAPTURE 12
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#define XHI_CMD_DESYNCH 13
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#define XHI_CMD_IPROG 15 /* Only in Virtex5 */
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#define XHI_CMD_CRCC 16 /* Only in Virtex5 */
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#define XHI_CMD_LTIMER 17 /* Only in Virtex5 */
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/* Packet constants */
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#define XHI_SYNC_PACKET 0xAA995566UL
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#define XHI_DUMMY_PACKET 0xFFFFFFFFUL
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#define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT)
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#define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
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(XHI_OP_READ << XHI_OP_SHIFT))
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#define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
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(XHI_OP_WRITE << XHI_OP_SHIFT))
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#define XHI_TYPE2_CNT_MASK 0x07FFFFFF
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#define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
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#define XHI_TYPE_1_HEADER_BYTES 4
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#define XHI_TYPE_2_HEADER_BYTES 8
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/* Constant to use for CRC check when CRC has been disabled */
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#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
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/* Meanings of the bits returned by get_status */
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#define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */
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#define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */
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#define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */
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#define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */
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#define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */
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/**
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* hwicap_type_1_read - Generates a Type 1 read packet header.
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* @reg: is the address of the register to be read back.
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*
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* Generates a Type 1 read packet header, which is used to indirectly
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* read registers in the configuration logic. This packet must then
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* be sent through the icap device, and a return packet received with
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* the information.
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**/
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static inline u32 hwicap_type_1_read(u32 reg)
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{
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return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
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(reg << XHI_REGISTER_SHIFT) |
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(XHI_OP_READ << XHI_OP_SHIFT);
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}
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/**
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* hwicap_type_1_write - Generates a Type 1 write packet header
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* @reg: is the address of the register to be read back.
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**/
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static inline u32 hwicap_type_1_write(u32 reg)
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{
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return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
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(reg << XHI_REGISTER_SHIFT) |
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(XHI_OP_WRITE << XHI_OP_SHIFT);
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}
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#endif
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