311 lines
8.5 KiB
C
311 lines
8.5 KiB
C
/*
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* OMAP4 Power domains framework
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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* Copyright (C) 2009 Nokia Corporation
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*
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* Abhijit Pagare (abhijitpagare@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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* Paul Walmsley
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
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#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
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#include <plat/powerdomain.h>
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#include "prcm-common.h"
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#include "cm.h"
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#include "cm-regbits-44xx.h"
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#include "prm.h"
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#include "prm-regbits-44xx.h"
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#if defined(CONFIG_ARCH_OMAP4)
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/* core_44xx_pwrdm: CORE power domain */
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static struct powerdomain core_44xx_pwrdm = {
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.name = "core_pwrdm",
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.prcm_offs = OMAP4430_PRM_CORE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 5,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* core_nret_bank */
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[1] = PWRSTS_OFF_RET, /* core_ocmram */
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[2] = PWRDM_POWER_RET, /* core_other_bank */
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[3] = PWRSTS_OFF_RET, /* ducati_l2ram */
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[4] = PWRSTS_OFF_RET, /* ducati_unicache */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* core_nret_bank */
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[1] = PWRSTS_OFF_RET, /* core_ocmram */
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[2] = PWRDM_POWER_ON, /* core_other_bank */
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[3] = PWRDM_POWER_ON, /* ducati_l2ram */
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[4] = PWRDM_POWER_ON, /* ducati_unicache */
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},
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};
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/* gfx_44xx_pwrdm: 3D accelerator power domain */
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static struct powerdomain gfx_44xx_pwrdm = {
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.name = "gfx_pwrdm",
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.prcm_offs = OMAP4430_PRM_GFX_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* gfx_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* gfx_mem */
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},
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};
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/* abe_44xx_pwrdm: Audio back end power domain */
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static struct powerdomain abe_44xx_pwrdm = {
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.name = "abe_pwrdm",
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.prcm_offs = OMAP4430_PRM_ABE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_OFF,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* aessmem */
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[1] = PWRDM_POWER_OFF, /* periphmem */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* aessmem */
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[1] = PWRDM_POWER_ON, /* periphmem */
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},
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};
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/* dss_44xx_pwrdm: Display subsystem power domain */
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static struct powerdomain dss_44xx_pwrdm = {
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.name = "dss_pwrdm",
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.prcm_offs = OMAP4430_PRM_DSS_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* dss_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* dss_mem */
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},
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};
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/* tesla_44xx_pwrdm: Tesla processor power domain */
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static struct powerdomain tesla_44xx_pwrdm = {
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.name = "tesla_pwrdm",
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.prcm_offs = OMAP4430_PRM_TESLA_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 3,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_RET, /* tesla_edma */
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[1] = PWRSTS_OFF_RET, /* tesla_l1 */
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[2] = PWRSTS_OFF_RET, /* tesla_l2 */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* tesla_edma */
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[1] = PWRDM_POWER_ON, /* tesla_l1 */
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[2] = PWRDM_POWER_ON, /* tesla_l2 */
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},
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};
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/* wkup_44xx_pwrdm: Wake-up power domain */
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static struct powerdomain wkup_44xx_pwrdm = {
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.name = "wkup_pwrdm",
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.prcm_offs = OMAP4430_PRM_WKUP_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRDM_POWER_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* wkup_bank */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* wkup_bank */
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},
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};
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/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
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static struct powerdomain cpu0_44xx_pwrdm = {
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.name = "cpu0_pwrdm",
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.prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* cpu0_l1 */
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},
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};
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/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
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static struct powerdomain cpu1_44xx_pwrdm = {
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.name = "cpu1_pwrdm",
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.prcm_offs = OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* cpu1_l1 */
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},
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};
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/* emu_44xx_pwrdm: Emulation power domain */
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static struct powerdomain emu_44xx_pwrdm = {
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.name = "emu_pwrdm",
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.prcm_offs = OMAP4430_PRM_EMU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* emu_bank */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* emu_bank */
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},
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};
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/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
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static struct powerdomain mpu_44xx_pwrdm = {
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.name = "mpu_pwrdm",
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.prcm_offs = OMAP4430_PRM_MPU_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 3,
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* mpu_l1 */
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[1] = PWRSTS_OFF_RET, /* mpu_l2 */
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[2] = PWRDM_POWER_RET, /* mpu_ram */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* mpu_l1 */
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[1] = PWRDM_POWER_ON, /* mpu_l2 */
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[2] = PWRDM_POWER_ON, /* mpu_ram */
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},
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};
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/* ivahd_44xx_pwrdm: IVA-HD power domain */
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static struct powerdomain ivahd_44xx_pwrdm = {
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.name = "ivahd_pwrdm",
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.prcm_offs = OMAP4430_PRM_IVAHD_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRDM_POWER_OFF,
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.banks = 4,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* hwa_mem */
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[1] = PWRSTS_OFF_RET, /* sl2_mem */
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[2] = PWRSTS_OFF_RET, /* tcm1_mem */
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[3] = PWRSTS_OFF_RET, /* tcm2_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* hwa_mem */
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[1] = PWRDM_POWER_ON, /* sl2_mem */
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[2] = PWRDM_POWER_ON, /* tcm1_mem */
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[3] = PWRDM_POWER_ON, /* tcm2_mem */
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},
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};
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/* cam_44xx_pwrdm: Camera subsystem power domain */
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static struct powerdomain cam_44xx_pwrdm = {
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.name = "cam_pwrdm",
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.prcm_offs = OMAP4430_PRM_CAM_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_ON,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* cam_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* cam_mem */
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},
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};
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/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
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static struct powerdomain l3init_44xx_pwrdm = {
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.name = "l3init_pwrdm",
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.prcm_offs = OMAP4430_PRM_L3INIT_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 1,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* l3init_bank1 */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* l3init_bank1 */
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},
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};
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/* l4per_44xx_pwrdm: Target peripherals power domain */
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static struct powerdomain l4per_44xx_pwrdm = {
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.name = "l4per_pwrdm",
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.prcm_offs = OMAP4430_PRM_L4PER_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.banks = 2,
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.pwrsts_mem_ret = {
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[0] = PWRDM_POWER_OFF, /* nonretained_bank */
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[1] = PWRDM_POWER_RET, /* retained_bank */
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},
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.pwrsts_mem_on = {
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[0] = PWRDM_POWER_ON, /* nonretained_bank */
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[1] = PWRDM_POWER_ON, /* retained_bank */
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},
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};
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/*
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* always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
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* domain
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*/
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static struct powerdomain always_on_core_44xx_pwrdm = {
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.name = "always_on_core_pwrdm",
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.prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRDM_POWER_ON,
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};
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/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
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static struct powerdomain cefuse_44xx_pwrdm = {
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.name = "cefuse_pwrdm",
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.prcm_offs = OMAP4430_PRM_CEFUSE_MOD,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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.pwrsts = PWRSTS_OFF_ON,
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};
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/*
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* The following power domains are not under SW control
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*
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* always_on_iva
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* always_on_mpu
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* stdefuse
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*/
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#endif
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#endif
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