532 lines
13 KiB
C
532 lines
13 KiB
C
/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "qed.h"
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#include "qed_hsi.h"
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#include "qed_hw.h"
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#include "qed_init_ops.h"
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#include "qed_reg_addr.h"
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#define QED_INIT_MAX_POLL_COUNT 100
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#define QED_INIT_POLL_PERIOD_US 500
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static u32 pxp_global_win[] = {
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0,
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0,
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0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
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0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
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0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
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0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
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0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */
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0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */
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0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */
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0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */
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0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */
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0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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};
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void qed_init_iro_array(struct qed_dev *cdev)
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{
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cdev->iro_arr = iro_arr;
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}
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/* Runtime configuration helpers */
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void qed_init_clear_rt_data(struct qed_hwfn *p_hwfn)
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{
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int i;
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for (i = 0; i < RUNTIME_ARRAY_SIZE; i++)
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p_hwfn->rt_data[i].b_valid = false;
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}
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void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn,
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u32 rt_offset,
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u32 val)
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{
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p_hwfn->rt_data[rt_offset].init_val = val;
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p_hwfn->rt_data[rt_offset].b_valid = true;
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}
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void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn,
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u32 rt_offset,
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u32 *val,
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size_t size)
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{
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size_t i;
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for (i = 0; i < size / sizeof(u32); i++) {
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p_hwfn->rt_data[rt_offset + i].init_val = val[i];
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p_hwfn->rt_data[rt_offset + i].b_valid = true;
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}
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}
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static void qed_init_rt(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr,
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u32 rt_offset,
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u32 size)
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{
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struct qed_rt_data *rt_data = p_hwfn->rt_data + rt_offset;
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u32 i;
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for (i = 0; i < size; i++) {
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if (!rt_data[i].b_valid)
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continue;
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qed_wr(p_hwfn, p_ptt, addr + (i << 2), rt_data[i].init_val);
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}
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}
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int qed_init_alloc(struct qed_hwfn *p_hwfn)
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{
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struct qed_rt_data *rt_data;
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rt_data = kzalloc(sizeof(*rt_data) * RUNTIME_ARRAY_SIZE, GFP_ATOMIC);
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if (!rt_data)
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return -ENOMEM;
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p_hwfn->rt_data = rt_data;
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return 0;
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}
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void qed_init_free(struct qed_hwfn *p_hwfn)
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{
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kfree(p_hwfn->rt_data);
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p_hwfn->rt_data = NULL;
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}
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static int qed_init_array_dmae(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr,
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u32 dmae_data_offset,
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u32 size,
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const u32 *buf,
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bool b_must_dmae,
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bool b_can_dmae)
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{
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int rc = 0;
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/* Perform DMAE only for lengthy enough sections or for wide-bus */
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if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
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const u32 *data = buf + dmae_data_offset;
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u32 i;
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for (i = 0; i < size; i++)
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qed_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
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} else {
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rc = qed_dmae_host2grc(p_hwfn, p_ptt,
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(uintptr_t)(buf + dmae_data_offset),
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addr, size, 0);
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}
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return rc;
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}
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static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr,
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u32 fill,
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u32 fill_count)
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{
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static u32 zero_buffer[DMAE_MAX_RW_SIZE];
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memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
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/* invoke the DMAE virtual/physical buffer API with
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* 1. DMAE init channel
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* 2. addr,
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* 3. p_hwfb->temp_data,
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* 4. fill_count
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*/
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return qed_dmae_host2grc(p_hwfn, p_ptt,
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(uintptr_t)(&zero_buffer[0]),
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addr, fill_count,
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QED_DMAE_FLAG_RW_REPL_SRC);
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}
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static void qed_init_fill(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr,
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u32 fill,
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u32 fill_count)
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{
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u32 i;
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for (i = 0; i < fill_count; i++, addr += sizeof(u32))
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qed_wr(p_hwfn, p_ptt, addr, fill);
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}
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static int qed_init_cmd_array(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct init_write_op *cmd,
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bool b_must_dmae,
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bool b_can_dmae)
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{
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u32 data = le32_to_cpu(cmd->data);
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u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
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u32 dmae_array_offset = le32_to_cpu(cmd->args.array_offset);
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u32 offset, output_len, input_len, max_size;
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struct qed_dev *cdev = p_hwfn->cdev;
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union init_array_hdr *hdr;
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const u32 *array_data;
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int rc = 0;
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u32 size;
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array_data = cdev->fw_data->arr_data;
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hdr = (union init_array_hdr *)(array_data +
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dmae_array_offset);
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data = le32_to_cpu(hdr->raw.data);
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switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
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case INIT_ARR_ZIPPED:
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offset = dmae_array_offset + 1;
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input_len = GET_FIELD(data,
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INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
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max_size = MAX_ZIPPED_SIZE * 4;
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memset(p_hwfn->unzip_buf, 0, max_size);
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output_len = qed_unzip_data(p_hwfn, input_len,
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(u8 *)&array_data[offset],
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max_size, (u8 *)p_hwfn->unzip_buf);
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if (output_len) {
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rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 0,
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output_len,
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p_hwfn->unzip_buf,
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b_must_dmae, b_can_dmae);
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} else {
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DP_NOTICE(p_hwfn, "Failed to unzip dmae data\n");
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rc = -EINVAL;
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}
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break;
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case INIT_ARR_PATTERN:
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{
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u32 repeats = GET_FIELD(data,
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INIT_ARRAY_PATTERN_HDR_REPETITIONS);
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u32 i;
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size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
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for (i = 0; i < repeats; i++, addr += size << 2) {
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rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
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dmae_array_offset + 1,
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size, array_data,
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b_must_dmae, b_can_dmae);
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if (rc)
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break;
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}
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break;
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}
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case INIT_ARR_STANDARD:
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size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
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rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
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dmae_array_offset + 1,
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size, array_data,
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b_must_dmae, b_can_dmae);
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break;
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}
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return rc;
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}
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/* init_ops write command */
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static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct init_write_op *cmd,
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bool b_can_dmae)
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{
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u32 data = le32_to_cpu(cmd->data);
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u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
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bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
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union init_write_args *arg = &cmd->args;
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int rc = 0;
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/* Sanitize */
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if (b_must_dmae && !b_can_dmae) {
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DP_NOTICE(p_hwfn,
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"Need to write to %08x for Wide-bus but DMAE isn't allowed\n",
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addr);
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return -EINVAL;
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}
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switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
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case INIT_SRC_INLINE:
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qed_wr(p_hwfn, p_ptt, addr,
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le32_to_cpu(arg->inline_val));
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break;
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case INIT_SRC_ZEROS:
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if (b_must_dmae ||
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(b_can_dmae && (le32_to_cpu(arg->zeros_count) >= 64)))
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rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0,
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le32_to_cpu(arg->zeros_count));
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else
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qed_init_fill(p_hwfn, p_ptt, addr, 0,
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le32_to_cpu(arg->zeros_count));
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break;
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case INIT_SRC_ARRAY:
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rc = qed_init_cmd_array(p_hwfn, p_ptt, cmd,
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b_must_dmae, b_can_dmae);
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break;
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case INIT_SRC_RUNTIME:
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qed_init_rt(p_hwfn, p_ptt, addr,
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le16_to_cpu(arg->runtime.offset),
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le16_to_cpu(arg->runtime.size));
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break;
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}
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return rc;
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}
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static inline bool comp_eq(u32 val, u32 expected_val)
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{
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return val == expected_val;
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}
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static inline bool comp_and(u32 val, u32 expected_val)
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{
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return (val & expected_val) == expected_val;
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}
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static inline bool comp_or(u32 val, u32 expected_val)
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{
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return (val | expected_val) > 0;
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}
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/* init_ops read/poll commands */
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static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct init_read_op *cmd)
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{
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u32 data = le32_to_cpu(cmd->op_data);
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u32 addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
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bool (*comp_check)(u32 val,
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u32 expected_val);
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u32 delay = QED_INIT_POLL_PERIOD_US, val;
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val = qed_rd(p_hwfn, p_ptt, addr);
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data = le32_to_cpu(cmd->op_data);
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if (GET_FIELD(data, INIT_READ_OP_POLL)) {
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int i;
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switch (GET_FIELD(data, INIT_READ_OP_POLL_COMP)) {
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case INIT_COMPARISON_EQ:
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comp_check = comp_eq;
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break;
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case INIT_COMPARISON_OR:
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comp_check = comp_or;
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break;
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case INIT_COMPARISON_AND:
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comp_check = comp_and;
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break;
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default:
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comp_check = NULL;
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DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
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data);
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return;
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}
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for (i = 0;
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i < QED_INIT_MAX_POLL_COUNT &&
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!comp_check(val, le32_to_cpu(cmd->expected_val));
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i++) {
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udelay(delay);
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val = qed_rd(p_hwfn, p_ptt, addr);
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}
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if (i == QED_INIT_MAX_POLL_COUNT)
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DP_ERR(p_hwfn,
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"Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparsion %08x)]\n",
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addr, le32_to_cpu(cmd->expected_val),
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val, data);
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}
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}
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/* init_ops callbacks entry point */
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static void qed_init_cmd_cb(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct init_callback_op *p_cmd)
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{
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DP_NOTICE(p_hwfn, "Currently init values have no need of callbacks\n");
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}
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static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn,
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u16 *offset,
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int modes)
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{
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struct qed_dev *cdev = p_hwfn->cdev;
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const u8 *modes_tree_buf;
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u8 arg1, arg2, tree_val;
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modes_tree_buf = cdev->fw_data->modes_tree_buf;
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tree_val = modes_tree_buf[(*offset)++];
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switch (tree_val) {
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case INIT_MODE_OP_NOT:
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return qed_init_cmd_mode_match(p_hwfn, offset, modes) ^ 1;
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case INIT_MODE_OP_OR:
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arg1 = qed_init_cmd_mode_match(p_hwfn, offset, modes);
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arg2 = qed_init_cmd_mode_match(p_hwfn, offset, modes);
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return arg1 | arg2;
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case INIT_MODE_OP_AND:
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arg1 = qed_init_cmd_mode_match(p_hwfn, offset, modes);
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arg2 = qed_init_cmd_mode_match(p_hwfn, offset, modes);
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return arg1 & arg2;
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default:
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tree_val -= MAX_INIT_MODE_OPS;
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return (modes & (1 << tree_val)) ? 1 : 0;
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}
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}
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static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn,
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struct init_if_mode_op *p_cmd,
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int modes)
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{
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u16 offset = le16_to_cpu(p_cmd->modes_buf_offset);
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if (qed_init_cmd_mode_match(p_hwfn, &offset, modes))
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return 0;
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else
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return GET_FIELD(le32_to_cpu(p_cmd->op_data),
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INIT_IF_MODE_OP_CMD_OFFSET);
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}
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static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn,
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struct init_if_phase_op *p_cmd,
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u32 phase,
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u32 phase_id)
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{
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u32 data = le32_to_cpu(p_cmd->phase_data);
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u32 op_data = le32_to_cpu(p_cmd->op_data);
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if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
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(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
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GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
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return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET);
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else
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return 0;
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}
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int qed_init_run(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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int phase,
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int phase_id,
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int modes)
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{
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struct qed_dev *cdev = p_hwfn->cdev;
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u32 cmd_num, num_init_ops;
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union init_op *init_ops;
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bool b_dmae = false;
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int rc = 0;
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num_init_ops = cdev->fw_data->init_ops_size;
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init_ops = cdev->fw_data->init_ops;
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p_hwfn->unzip_buf = kzalloc(MAX_ZIPPED_SIZE * 4, GFP_ATOMIC);
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if (!p_hwfn->unzip_buf) {
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DP_NOTICE(p_hwfn, "Failed to allocate unzip buffer\n");
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return -ENOMEM;
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}
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for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
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union init_op *cmd = &init_ops[cmd_num];
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u32 data = le32_to_cpu(cmd->raw.op_data);
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switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
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case INIT_OP_WRITE:
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rc = qed_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
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b_dmae);
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break;
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case INIT_OP_READ:
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qed_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
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break;
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case INIT_OP_IF_MODE:
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cmd_num += qed_init_cmd_mode(p_hwfn, &cmd->if_mode,
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modes);
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break;
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case INIT_OP_IF_PHASE:
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cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
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phase, phase_id);
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b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE);
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break;
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case INIT_OP_DELAY:
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/* qed_init_run is always invoked from
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* sleep-able context
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*/
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udelay(le32_to_cpu(cmd->delay.delay));
|
|
break;
|
|
|
|
case INIT_OP_CALLBACK:
|
|
qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
|
|
break;
|
|
}
|
|
|
|
if (rc)
|
|
break;
|
|
}
|
|
|
|
kfree(p_hwfn->unzip_buf);
|
|
return rc;
|
|
}
|
|
|
|
void qed_gtt_init(struct qed_hwfn *p_hwfn)
|
|
{
|
|
u32 gtt_base;
|
|
u32 i;
|
|
|
|
/* Set the global windows */
|
|
gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pxp_global_win); i++)
|
|
if (pxp_global_win[i])
|
|
REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
|
|
pxp_global_win[i]);
|
|
}
|
|
|
|
int qed_init_fw_data(struct qed_dev *cdev,
|
|
const u8 *data)
|
|
{
|
|
struct qed_fw_data *fw = cdev->fw_data;
|
|
struct bin_buffer_hdr *buf_hdr;
|
|
u32 offset, len;
|
|
|
|
if (!data) {
|
|
DP_NOTICE(cdev, "Invalid fw data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
buf_hdr = (struct bin_buffer_hdr *)data;
|
|
|
|
offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
|
|
fw->init_ops = (union init_op *)(data + offset);
|
|
|
|
offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
|
|
fw->arr_data = (u32 *)(data + offset);
|
|
|
|
offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
|
|
fw->modes_tree_buf = (u8 *)(data + offset);
|
|
len = buf_hdr[BIN_BUF_INIT_CMD].length;
|
|
fw->init_ops_size = len / sizeof(struct init_raw_op);
|
|
|
|
return 0;
|
|
}
|