353 lines
8.1 KiB
C
353 lines
8.1 KiB
C
/*
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* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/gpio.h>
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#define PCI_VENDOR_ID_ROHM 0x10DB
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struct ioh_reg_comn {
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u32 ien;
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u32 istatus;
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u32 idisp;
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u32 iclr;
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u32 imask;
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u32 imaskclr;
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u32 po;
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u32 pi;
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u32 pm;
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u32 im_0;
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u32 im_1;
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u32 reserved;
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};
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struct ioh_regs {
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struct ioh_reg_comn regs[8];
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u32 reserve1[16];
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u32 ioh_sel_reg[4];
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u32 reserve2[11];
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u32 srst;
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};
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/**
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* struct ioh_gpio_reg_data - The register store data.
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* @po_reg: To store contents of PO register.
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* @pm_reg: To store contents of PM register.
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*/
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struct ioh_gpio_reg_data {
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u32 po_reg;
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u32 pm_reg;
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};
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/**
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* struct ioh_gpio - GPIO private data structure.
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* @base: PCI base address of Memory mapped I/O register.
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* @reg: Memory mapped IOH GPIO register list.
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* @dev: Pointer to device structure.
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* @gpio: Data for GPIO infrastructure.
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* @ioh_gpio_reg: Memory mapped Register data is saved here
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* when suspend.
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* @ch: Indicate GPIO channel
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*/
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struct ioh_gpio {
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void __iomem *base;
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struct ioh_regs __iomem *reg;
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struct device *dev;
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struct gpio_chip gpio;
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struct ioh_gpio_reg_data ioh_gpio_reg;
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struct mutex lock;
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int ch;
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};
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static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
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static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
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{
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u32 reg_val;
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struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
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mutex_lock(&chip->lock);
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reg_val = ioread32(&chip->reg->regs[chip->ch].po);
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if (val)
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reg_val |= (1 << nr);
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else
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reg_val &= ~(1 << nr);
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iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
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mutex_unlock(&chip->lock);
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}
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static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
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{
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struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
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return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
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}
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static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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int val)
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{
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struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
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u32 pm;
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u32 reg_val;
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mutex_lock(&chip->lock);
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pm = ioread32(&chip->reg->regs[chip->ch].pm) &
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((1 << num_ports[chip->ch]) - 1);
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pm |= (1 << nr);
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iowrite32(pm, &chip->reg->regs[chip->ch].pm);
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reg_val = ioread32(&chip->reg->regs[chip->ch].po);
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if (val)
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reg_val |= (1 << nr);
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else
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reg_val &= ~(1 << nr);
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mutex_unlock(&chip->lock);
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return 0;
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}
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static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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{
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struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
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u32 pm;
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mutex_lock(&chip->lock);
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pm = ioread32(&chip->reg->regs[chip->ch].pm) &
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((1 << num_ports[chip->ch]) - 1);
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pm &= ~(1 << nr);
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iowrite32(pm, &chip->reg->regs[chip->ch].pm);
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mutex_unlock(&chip->lock);
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return 0;
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}
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/*
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* Save register configuration and disable interrupts.
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*/
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static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
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{
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chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
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chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
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}
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/*
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* This function restores the register configuration of the GPIO device.
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*/
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static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
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{
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/* to store contents of PO register */
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iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
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/* to store contents of PM register */
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iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
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}
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static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
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{
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struct gpio_chip *gpio = &chip->gpio;
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gpio->label = dev_name(chip->dev);
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gpio->owner = THIS_MODULE;
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gpio->direction_input = ioh_gpio_direction_input;
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gpio->get = ioh_gpio_get;
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gpio->direction_output = ioh_gpio_direction_output;
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gpio->set = ioh_gpio_set;
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gpio->dbg_show = NULL;
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gpio->base = -1;
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gpio->ngpio = num_port;
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gpio->can_sleep = 0;
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}
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static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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int ret;
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int i;
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struct ioh_gpio *chip;
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void __iomem *base;
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void __iomem *chip_save;
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
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goto err_pci_enable;
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}
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ret = pci_request_regions(pdev, KBUILD_MODNAME);
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if (ret) {
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dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
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goto err_request_regions;
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}
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base = pci_iomap(pdev, 1, 0);
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if (base == 0) {
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dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
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ret = -ENOMEM;
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goto err_iomap;
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}
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chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
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if (chip_save == NULL) {
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dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
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ret = -ENOMEM;
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goto err_kzalloc;
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}
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chip = chip_save;
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for (i = 0; i < 8; i++, chip++) {
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chip->dev = &pdev->dev;
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chip->base = base;
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chip->reg = chip->base;
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chip->ch = i;
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mutex_init(&chip->lock);
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ioh_gpio_setup(chip, num_ports[i]);
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ret = gpiochip_add(&chip->gpio);
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if (ret) {
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dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
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goto err_gpiochip_add;
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}
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}
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chip = chip_save;
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pci_set_drvdata(pdev, chip);
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return 0;
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err_gpiochip_add:
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for (; i != 0; i--) {
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chip--;
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ret = gpiochip_remove(&chip->gpio);
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if (ret)
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dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
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}
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kfree(chip_save);
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err_kzalloc:
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pci_iounmap(pdev, base);
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err_iomap:
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pci_release_regions(pdev);
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err_request_regions:
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pci_disable_device(pdev);
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err_pci_enable:
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dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
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return ret;
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}
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static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
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{
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int err;
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int i;
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struct ioh_gpio *chip = pci_get_drvdata(pdev);
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void __iomem *chip_save;
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chip_save = chip;
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for (i = 0; i < 8; i++, chip++) {
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err = gpiochip_remove(&chip->gpio);
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if (err)
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dev_err(&pdev->dev, "Failed gpiochip_remove\n");
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}
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chip = chip_save;
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pci_iounmap(pdev, chip->base);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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kfree(chip);
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}
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#ifdef CONFIG_PM
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static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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s32 ret;
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struct ioh_gpio *chip = pci_get_drvdata(pdev);
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ioh_gpio_save_reg_conf(chip);
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ioh_gpio_restore_reg_conf(chip);
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ret = pci_save_state(pdev);
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if (ret) {
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dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
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return ret;
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}
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D0);
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ret = pci_enable_wake(pdev, PCI_D0, 1);
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if (ret)
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dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
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return 0;
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}
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static int ioh_gpio_resume(struct pci_dev *pdev)
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{
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s32 ret;
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struct ioh_gpio *chip = pci_get_drvdata(pdev);
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ret = pci_enable_wake(pdev, PCI_D0, 0);
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pci_set_power_state(pdev, PCI_D0);
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
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return ret;
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}
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pci_restore_state(pdev);
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iowrite32(0x01, &chip->reg->srst);
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iowrite32(0x00, &chip->reg->srst);
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ioh_gpio_restore_reg_conf(chip);
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return 0;
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}
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#else
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#define ioh_gpio_suspend NULL
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#define ioh_gpio_resume NULL
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#endif
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static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
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{ 0, }
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};
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static struct pci_driver ioh_gpio_driver = {
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.name = "ml_ioh_gpio",
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.id_table = ioh_gpio_pcidev_id,
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.probe = ioh_gpio_probe,
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.remove = __devexit_p(ioh_gpio_remove),
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.suspend = ioh_gpio_suspend,
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.resume = ioh_gpio_resume
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};
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static int __init ioh_gpio_pci_init(void)
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{
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return pci_register_driver(&ioh_gpio_driver);
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}
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module_init(ioh_gpio_pci_init);
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static void __exit ioh_gpio_pci_exit(void)
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{
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pci_unregister_driver(&ioh_gpio_driver);
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}
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module_exit(ioh_gpio_pci_exit);
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MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
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MODULE_LICENSE("GPL");
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