208 lines
5.3 KiB
Plaintext
208 lines
5.3 KiB
Plaintext
/*
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* P5040DS Device Tree Source
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* This software is provided by Freescale Semiconductor "as is" and any
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* express or implied warranties, including, but not limited to, the implied
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* warranties of merchantability and fitness for a particular purpose are
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* disclaimed. In no event shall Freescale Semiconductor be liable for any
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* direct, indirect, incidental, special, exemplary, or consequential damages
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* (including, but not limited to, procurement of substitute goods or services;
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* loss of use, data, or profits; or business interruption) however caused and
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* on any theory of liability, whether in contract, strict liability, or tort
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* (including negligence or otherwise) arising in any way out of the use of this
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* software, even if advised of the possibility of such damage.
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*/
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/include/ "fsl/p5040si-pre.dtsi"
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/ {
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model = "fsl,P5040DS";
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compatible = "fsl,P5040DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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memory {
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device_type = "memory";
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01008000>;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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};
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partition@kernel {
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label = "kernel";
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reg = <0x00100000 0x00500000>;
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};
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partition@dtb {
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label = "dtb";
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reg = <0x00600000 0x00100000>;
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};
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partition@fs {
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label = "file system";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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i2c@118100 {
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eeprom@51 {
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compatible = "at24,24c256";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "at24,24c256";
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reg = <0x52>;
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};
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};
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i2c@119100 {
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0x1 0x1 0 0>;
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};
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adt7461@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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};
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};
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lbc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x1000>;
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ranges = <0 0 0xf 0xe8000000 0x08000000
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2 0 0xf 0xffa00000 0x00040000
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3 0 0xf 0xffdf0000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x08000000>;
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bank-width = <2>;
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device-width = <2>;
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,elbc-fcm-nand";
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reg = <0x2 0x0 0x40000>;
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partition@0 {
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label = "NAND U-Boot Image";
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reg = <0x0 0x02000000>;
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};
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partition@2000000 {
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label = "NAND Root File System";
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reg = <0x02000000 0x10000000>;
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};
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partition@12000000 {
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label = "NAND Compressed RFS Image";
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reg = <0x12000000 0x08000000>;
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};
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partition@1a000000 {
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label = "NAND Linux Kernel Image";
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reg = <0x1a000000 0x04000000>;
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};
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partition@1e000000 {
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label = "NAND DTB Image";
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reg = <0x1e000000 0x01000000>;
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};
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partition@1f000000 {
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label = "NAND Writable User area";
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reg = <0x1f000000 0x01000000>;
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};
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};
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board-control@3,0 {
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compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
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reg = <3 0 0x40>;
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};
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};
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pci0: pcie@ffe200000 {
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reg = <0xf 0xfe200000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci1: pcie@ffe201000 {
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reg = <0xf 0xfe201000 0 0x1000>;
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ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci2: pcie@ffe202000 {
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reg = <0xf 0xfe202000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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};
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/include/ "fsl/p5040si-post.dtsi"
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