189 lines
5.6 KiB
C
189 lines
5.6 KiB
C
#ifndef __CARD_DDCB_H__
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#define __CARD_DDCB_H__
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/**
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* IBM Accelerator Family 'GenWQE'
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*
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* (C) Copyright IBM Corp. 2013
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*
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* Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
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* Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
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* Author: Michael Jung <mijung@gmx.net>
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* Author: Michael Ruettger <michael@ibmra.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include "genwqe_driver.h"
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#include "card_base.h"
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/**
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* struct ddcb - Device Driver Control Block DDCB
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* @hsi: Hardware software interlock
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* @shi: Software hardware interlock. Hsi and shi are used to interlock
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* software and hardware activities. We are using a compare and
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* swap operation to ensure that there are no races when
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* activating new DDCBs on the queue, or when we need to
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* purge a DDCB from a running queue.
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* @acfunc: Accelerator function addresses a unit within the chip
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* @cmd: Command to work on
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* @cmdopts_16: Options for the command
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* @asiv: Input data
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* @asv: Output data
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*
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* The DDCB data format is big endian. Multiple consequtive DDBCs form
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* a DDCB queue.
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*/
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#define ASIV_LENGTH 104 /* Old specification without ATS field */
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#define ASIV_LENGTH_ATS 96 /* New specification with ATS field */
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#define ASV_LENGTH 64
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struct ddcb {
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union {
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__be32 icrc_hsi_shi_32; /* iCRC, Hardware/SW interlock */
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struct {
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__be16 icrc_16;
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u8 hsi;
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u8 shi;
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};
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};
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u8 pre; /* Preamble */
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u8 xdir; /* Execution Directives */
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__be16 seqnum_16; /* Sequence Number */
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u8 acfunc; /* Accelerator Function.. */
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u8 cmd; /* Command. */
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__be16 cmdopts_16; /* Command Options */
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u8 sur; /* Status Update Rate */
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u8 psp; /* Protection Section Pointer */
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__be16 rsvd_0e_16; /* Reserved invariant */
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__be64 fwiv_64; /* Firmware Invariant. */
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union {
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struct {
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__be64 ats_64; /* Address Translation Spec */
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u8 asiv[ASIV_LENGTH_ATS]; /* New ASIV */
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} n;
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u8 __asiv[ASIV_LENGTH]; /* obsolete */
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};
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u8 asv[ASV_LENGTH]; /* Appl Spec Variant */
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__be16 rsvd_c0_16; /* Reserved Variant */
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__be16 vcrc_16; /* Variant CRC */
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__be32 rsvd_32; /* Reserved unprotected */
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__be64 deque_ts_64; /* Deque Time Stamp. */
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__be16 retc_16; /* Return Code */
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__be16 attn_16; /* Attention/Extended Error Codes */
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__be32 progress_32; /* Progress indicator. */
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__be64 cmplt_ts_64; /* Completion Time Stamp. */
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/* The following layout matches the new service layer format */
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__be32 ibdc_32; /* Inbound Data Count (* 256) */
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__be32 obdc_32; /* Outbound Data Count (* 256) */
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__be64 rsvd_SLH_64; /* Reserved for hardware */
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union { /* private data for driver */
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u8 priv[8];
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__be64 priv_64;
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};
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__be64 disp_ts_64; /* Dispatch TimeStamp */
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} __attribute__((__packed__));
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/* CRC polynomials for DDCB */
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#define CRC16_POLYNOMIAL 0x1021
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/*
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* SHI: Software to Hardware Interlock
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* This 1 byte field is written by software to interlock the
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* movement of one queue entry to another with the hardware in the
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* chip.
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*/
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#define DDCB_SHI_INTR 0x04 /* Bit 2 */
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#define DDCB_SHI_PURGE 0x02 /* Bit 1 */
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#define DDCB_SHI_NEXT 0x01 /* Bit 0 */
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/*
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* HSI: Hardware to Software interlock
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* This 1 byte field is written by hardware to interlock the movement
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* of one queue entry to another with the software in the chip.
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*/
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#define DDCB_HSI_COMPLETED 0x40 /* Bit 6 */
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#define DDCB_HSI_FETCHED 0x04 /* Bit 2 */
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/*
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* Accessing HSI/SHI is done 32-bit wide
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* Normally 16-bit access would work too, but on some platforms the
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* 16 compare and swap operation is not supported. Therefore
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* switching to 32-bit such that those platforms will work too.
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*
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* iCRC HSI/SHI
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*/
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#define DDCB_INTR_BE32 cpu_to_be32(0x00000004)
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#define DDCB_PURGE_BE32 cpu_to_be32(0x00000002)
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#define DDCB_NEXT_BE32 cpu_to_be32(0x00000001)
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#define DDCB_COMPLETED_BE32 cpu_to_be32(0x00004000)
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#define DDCB_FETCHED_BE32 cpu_to_be32(0x00000400)
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/* Definitions of DDCB presets */
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#define DDCB_PRESET_PRE 0x80
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#define ICRC_LENGTH(n) ((n) + 8 + 8 + 8) /* used ASIV + hdr fields */
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#define VCRC_LENGTH(n) ((n)) /* used ASV */
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/*
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* Genwqe Scatter Gather list
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* Each element has up to 8 entries.
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* The chaining element is element 0 cause of prefetching needs.
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*/
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/*
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* 0b0110 Chained descriptor. The descriptor is describing the next
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* descriptor list.
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*/
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#define SG_CHAINED (0x6)
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/*
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* 0b0010 First entry of a descriptor list. Start from a Buffer-Empty
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* condition.
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*/
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#define SG_DATA (0x2)
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/*
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* 0b0000 Early terminator. This is the last entry on the list
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* irregardless of the length indicated.
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*/
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#define SG_END_LIST (0x0)
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/**
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* struct sglist - Scatter gather list
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* @target_addr: Either a dma addr of memory to work on or a
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* dma addr or a subsequent sglist block.
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* @len: Length of the data block.
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* @flags: See above.
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*
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* Depending on the command the GenWQE card can use a scatter gather
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* list to describe the memory it works on. Always 8 sg_entry's form
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* a block.
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*/
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struct sg_entry {
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__be64 target_addr;
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__be32 len;
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__be32 flags;
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};
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#endif /* __CARD_DDCB_H__ */
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