Tuomas Tynkkynen 0c59d26770 clk: tegra: Add binding for the Tegra124 DFLL clocksource ... The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual Tegra124 clock-and-reset controller, so it gets its own node in the device tree. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>		2015-07-16 09:32:43 +02:00
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bindings	clk: tegra: Add binding for the Tegra124 DFLL clocksource	2015-07-16 09:32:43 +02:00
00-INDEX	…
booting-without-of.txt	ARM: 8354/1: Documentation: devicetree: root node serial-number property documentation	2015-05-08 10:42:34 +01:00
changesets.txt	…
dynamic-resolution-notes.txt	of: Introduce Device Tree resolve support.	2014-10-04 21:24:26 +01:00
of_unittest.txt	Documentation: rename of_selftest.txt to of_unittest.txt	2015-03-25 00:50:53 -05:00
overlay-notes.txt	Documentation: devicetree: Fix double words in Doumentation/devicetree	2015-01-28 15:13:11 -07:00
todo.txt	of: Eliminate of_allnodes list	2014-11-04 13:29:38 +00:00
usage-model.txt	…