1612 lines
41 KiB
C
1612 lines
41 KiB
C
/*
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* Driver for Motorola IMX serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* Author: Sascha Hauer <sascha@saschahauer.de>
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* Copyright (C) 2004 Pengutronix
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*
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* Copyright (C) 2009 emlix GmbH
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* Author: Fabian Godehardt (added IrDA support for iMX)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* [29-Mar-2005] Mike Lee
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* Added hardware handshake
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*/
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#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/platform_device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/rational.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <linux/platform_data/serial-imx.h>
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/* Register definitions */
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#define URXD0 0x0 /* Receiver Register */
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#define URTX0 0x40 /* Transmitter Register */
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#define UCR1 0x80 /* Control Register 1 */
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#define UCR2 0x84 /* Control Register 2 */
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#define UCR3 0x88 /* Control Register 3 */
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#define UCR4 0x8c /* Control Register 4 */
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#define UFCR 0x90 /* FIFO Control Register */
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#define USR1 0x94 /* Status Register 1 */
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#define USR2 0x98 /* Status Register 2 */
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#define UESC 0x9c /* Escape Character Register */
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#define UTIM 0xa0 /* Escape Timer Register */
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#define UBIR 0xa4 /* BRM Incremental Register */
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#define UBMR 0xa8 /* BRM Modulator Register */
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#define UBRC 0xac /* Baud Rate Count Register */
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#define IMX21_ONEMS 0xb0 /* One Millisecond register */
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#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
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#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
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/* UART Control Register Bit Fields.*/
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#define URXD_CHARRDY (1<<15)
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#define URXD_ERR (1<<14)
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#define URXD_OVRRUN (1<<13)
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#define URXD_FRMERR (1<<12)
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#define URXD_BRK (1<<11)
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#define URXD_PRERR (1<<10)
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#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
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#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Recv data ready */
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#define UTS_FRCPERR (1<<13) /* Force parity error */
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#define UTS_LOOP (1<<12) /* Loop tx and rx */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_RXFULL (1<<3) /* RxFIFO full */
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#define UTS_SOFTRST (1<<0) /* Software reset */
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/* We've been assigned a range on the "Low-density serial ports" major */
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#define SERIAL_IMX_MAJOR 207
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#define MINOR_START 16
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#define DEV_NAME "ttymxc"
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/*
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* This determines how often we check the modem status signals
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* for any change. They generally aren't connected to an IRQ
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* so we have to poll them. We also check immediately before
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* filling the TX fifo incase CTS has been dropped.
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*/
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#define MCTRL_TIMEOUT (250*HZ/1000)
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#define DRIVER_NAME "IMX-uart"
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#define UART_NR 8
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/* i.mx21 type uart runs on all i.mx except i.mx1 */
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enum imx_uart_type {
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IMX1_UART,
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IMX21_UART,
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};
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/* device type dependent stuff */
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struct imx_uart_data {
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unsigned uts_reg;
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enum imx_uart_type devtype;
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};
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struct imx_port {
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struct uart_port port;
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struct timer_list timer;
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unsigned int old_status;
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int txirq, rxirq, rtsirq;
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unsigned int have_rtscts:1;
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unsigned int use_irda:1;
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unsigned int irda_inv_rx:1;
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unsigned int irda_inv_tx:1;
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unsigned short trcv_delay; /* transceiver delay */
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struct clk *clk_ipg;
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struct clk *clk_per;
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const struct imx_uart_data *devdata;
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};
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struct imx_port_ucrs {
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unsigned int ucr1;
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unsigned int ucr2;
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unsigned int ucr3;
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};
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#ifdef CONFIG_IRDA
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#define USE_IRDA(sport) ((sport)->use_irda)
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#else
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#define USE_IRDA(sport) (0)
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#endif
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static struct imx_uart_data imx_uart_devdata[] = {
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[IMX1_UART] = {
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.uts_reg = IMX1_UTS,
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.devtype = IMX1_UART,
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},
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[IMX21_UART] = {
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.uts_reg = IMX21_UTS,
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.devtype = IMX21_UART,
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},
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};
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static struct platform_device_id imx_uart_devtype[] = {
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{
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.name = "imx1-uart",
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.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
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}, {
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.name = "imx21-uart",
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.driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
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static struct of_device_id imx_uart_dt_ids[] = {
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{ .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
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{ .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
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static inline unsigned uts_reg(struct imx_port *sport)
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{
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return sport->devdata->uts_reg;
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}
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static inline int is_imx1_uart(struct imx_port *sport)
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{
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return sport->devdata->devtype == IMX1_UART;
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}
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static inline int is_imx21_uart(struct imx_port *sport)
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{
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return sport->devdata->devtype == IMX21_UART;
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}
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/*
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* Handle any change of modem status signal since we were last called.
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*/
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static void imx_mctrl_check(struct imx_port *sport)
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{
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unsigned int status, changed;
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status = sport->port.ops->get_mctrl(&sport->port);
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changed = status ^ sport->old_status;
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if (changed == 0)
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return;
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sport->old_status = status;
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if (changed & TIOCM_RI)
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sport->port.icount.rng++;
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if (changed & TIOCM_DSR)
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sport->port.icount.dsr++;
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if (changed & TIOCM_CAR)
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uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
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if (changed & TIOCM_CTS)
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uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
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wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
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}
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/*
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* This is our per-port timeout handler, for checking the
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* modem status signals.
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*/
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static void imx_timeout(unsigned long data)
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{
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struct imx_port *sport = (struct imx_port *)data;
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unsigned long flags;
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if (sport->port.state) {
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spin_lock_irqsave(&sport->port.lock, flags);
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imx_mctrl_check(sport);
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spin_unlock_irqrestore(&sport->port.lock, flags);
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mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
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}
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}
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/*
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* interrupts disabled on entry
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*/
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static void imx_stop_tx(struct uart_port *port)
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{
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struct imx_port *sport = (struct imx_port *)port;
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unsigned long temp;
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if (USE_IRDA(sport)) {
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/* half duplex - wait for end of transmission */
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int n = 256;
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while ((--n > 0) &&
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!(readl(sport->port.membase + USR2) & USR2_TXDC)) {
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udelay(5);
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barrier();
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}
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/*
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* irda transceiver - wait a bit more to avoid
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* cutoff, hardware dependent
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*/
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udelay(sport->trcv_delay);
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/*
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* half duplex - reactivate receive mode,
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* flush receive pipe echo crap
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*/
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if (readl(sport->port.membase + USR2) & USR2_TXDC) {
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temp = readl(sport->port.membase + UCR1);
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temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
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writel(temp, sport->port.membase + UCR1);
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temp = readl(sport->port.membase + UCR4);
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temp &= ~(UCR4_TCEN);
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writel(temp, sport->port.membase + UCR4);
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while (readl(sport->port.membase + URXD0) &
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URXD_CHARRDY)
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barrier();
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temp = readl(sport->port.membase + UCR1);
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temp |= UCR1_RRDYEN;
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writel(temp, sport->port.membase + UCR1);
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temp = readl(sport->port.membase + UCR4);
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temp |= UCR4_DREN;
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writel(temp, sport->port.membase + UCR4);
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}
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return;
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}
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temp = readl(sport->port.membase + UCR1);
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writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
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}
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/*
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* interrupts disabled on entry
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*/
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static void imx_stop_rx(struct uart_port *port)
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{
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struct imx_port *sport = (struct imx_port *)port;
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unsigned long temp;
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temp = readl(sport->port.membase + UCR2);
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writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
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}
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/*
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* Set the modem control timer to fire immediately.
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*/
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static void imx_enable_ms(struct uart_port *port)
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{
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struct imx_port *sport = (struct imx_port *)port;
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mod_timer(&sport->timer, jiffies);
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}
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static inline void imx_transmit_buffer(struct imx_port *sport)
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{
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struct circ_buf *xmit = &sport->port.state->xmit;
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while (!uart_circ_empty(xmit) &&
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!(readl(sport->port.membase + uts_reg(sport))
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& UTS_TXFULL)) {
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/* send xmit->buf[xmit->tail]
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* out the port here */
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writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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sport->port.icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(&sport->port);
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if (uart_circ_empty(xmit))
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imx_stop_tx(&sport->port);
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}
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/*
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* interrupts disabled on entry
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*/
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static void imx_start_tx(struct uart_port *port)
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{
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struct imx_port *sport = (struct imx_port *)port;
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unsigned long temp;
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if (USE_IRDA(sport)) {
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/* half duplex in IrDA mode; have to disable receive mode */
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temp = readl(sport->port.membase + UCR4);
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temp &= ~(UCR4_DREN);
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writel(temp, sport->port.membase + UCR4);
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temp = readl(sport->port.membase + UCR1);
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temp &= ~(UCR1_RRDYEN);
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writel(temp, sport->port.membase + UCR1);
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}
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temp = readl(sport->port.membase + UCR1);
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writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
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if (USE_IRDA(sport)) {
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temp = readl(sport->port.membase + UCR1);
|
|
temp |= UCR1_TRDYEN;
|
|
writel(temp, sport->port.membase + UCR1);
|
|
|
|
temp = readl(sport->port.membase + UCR4);
|
|
temp |= UCR4_TCEN;
|
|
writel(temp, sport->port.membase + UCR4);
|
|
}
|
|
|
|
if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
|
|
imx_transmit_buffer(sport);
|
|
}
|
|
|
|
static irqreturn_t imx_rtsint(int irq, void *dev_id)
|
|
{
|
|
struct imx_port *sport = dev_id;
|
|
unsigned int val;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
|
|
writel(USR1_RTSD, sport->port.membase + USR1);
|
|
val = readl(sport->port.membase + USR1) & USR1_RTSS;
|
|
uart_handle_cts_change(&sport->port, !!val);
|
|
wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
|
|
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t imx_txint(int irq, void *dev_id)
|
|
{
|
|
struct imx_port *sport = dev_id;
|
|
struct circ_buf *xmit = &sport->port.state->xmit;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
if (sport->port.x_char) {
|
|
/* Send next char */
|
|
writel(sport->port.x_char, sport->port.membase + URTX0);
|
|
goto out;
|
|
}
|
|
|
|
if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
|
|
imx_stop_tx(&sport->port);
|
|
goto out;
|
|
}
|
|
|
|
imx_transmit_buffer(sport);
|
|
|
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
|
uart_write_wakeup(&sport->port);
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t imx_rxint(int irq, void *dev_id)
|
|
{
|
|
struct imx_port *sport = dev_id;
|
|
unsigned int rx, flg, ignored = 0;
|
|
struct tty_port *port = &sport->port.state->port;
|
|
unsigned long flags, temp;
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
|
|
while (readl(sport->port.membase + USR2) & USR2_RDR) {
|
|
flg = TTY_NORMAL;
|
|
sport->port.icount.rx++;
|
|
|
|
rx = readl(sport->port.membase + URXD0);
|
|
|
|
temp = readl(sport->port.membase + USR2);
|
|
if (temp & USR2_BRCD) {
|
|
writel(USR2_BRCD, sport->port.membase + USR2);
|
|
if (uart_handle_break(&sport->port))
|
|
continue;
|
|
}
|
|
|
|
if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
|
|
continue;
|
|
|
|
if (unlikely(rx & URXD_ERR)) {
|
|
if (rx & URXD_BRK)
|
|
sport->port.icount.brk++;
|
|
else if (rx & URXD_PRERR)
|
|
sport->port.icount.parity++;
|
|
else if (rx & URXD_FRMERR)
|
|
sport->port.icount.frame++;
|
|
if (rx & URXD_OVRRUN)
|
|
sport->port.icount.overrun++;
|
|
|
|
if (rx & sport->port.ignore_status_mask) {
|
|
if (++ignored > 100)
|
|
goto out;
|
|
continue;
|
|
}
|
|
|
|
rx &= sport->port.read_status_mask;
|
|
|
|
if (rx & URXD_BRK)
|
|
flg = TTY_BREAK;
|
|
else if (rx & URXD_PRERR)
|
|
flg = TTY_PARITY;
|
|
else if (rx & URXD_FRMERR)
|
|
flg = TTY_FRAME;
|
|
if (rx & URXD_OVRRUN)
|
|
flg = TTY_OVERRUN;
|
|
|
|
#ifdef SUPPORT_SYSRQ
|
|
sport->port.sysrq = 0;
|
|
#endif
|
|
}
|
|
|
|
tty_insert_flip_char(port, rx, flg);
|
|
}
|
|
|
|
out:
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
tty_flip_buffer_push(port);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t imx_int(int irq, void *dev_id)
|
|
{
|
|
struct imx_port *sport = dev_id;
|
|
unsigned int sts;
|
|
|
|
sts = readl(sport->port.membase + USR1);
|
|
|
|
if (sts & USR1_RRDY)
|
|
imx_rxint(irq, dev_id);
|
|
|
|
if (sts & USR1_TRDY &&
|
|
readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
|
|
imx_txint(irq, dev_id);
|
|
|
|
if (sts & USR1_RTSD)
|
|
imx_rtsint(irq, dev_id);
|
|
|
|
if (sts & USR1_AWAKE)
|
|
writel(USR1_AWAKE, sport->port.membase + USR1);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*
|
|
* Return TIOCSER_TEMT when transmitter is not busy.
|
|
*/
|
|
static unsigned int imx_tx_empty(struct uart_port *port)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
|
|
return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
|
|
}
|
|
|
|
/*
|
|
* We have a modem side uart, so the meanings of RTS and CTS are inverted.
|
|
*/
|
|
static unsigned int imx_get_mctrl(struct uart_port *port)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
|
|
|
|
if (readl(sport->port.membase + USR1) & USR1_RTSS)
|
|
tmp |= TIOCM_CTS;
|
|
|
|
if (readl(sport->port.membase + UCR2) & UCR2_CTS)
|
|
tmp |= TIOCM_RTS;
|
|
|
|
return tmp;
|
|
}
|
|
|
|
static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
unsigned long temp;
|
|
|
|
temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
|
|
|
|
if (mctrl & TIOCM_RTS)
|
|
temp |= UCR2_CTS;
|
|
|
|
writel(temp, sport->port.membase + UCR2);
|
|
}
|
|
|
|
/*
|
|
* Interrupts always disabled.
|
|
*/
|
|
static void imx_break_ctl(struct uart_port *port, int break_state)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
unsigned long flags, temp;
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
|
|
temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
|
|
|
|
if (break_state != 0)
|
|
temp |= UCR1_SNDBRK;
|
|
|
|
writel(temp, sport->port.membase + UCR1);
|
|
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
}
|
|
|
|
#define TXTL 2 /* reset default */
|
|
#define RXTL 1 /* reset default */
|
|
|
|
static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
|
|
{
|
|
unsigned int val;
|
|
|
|
/* set receiver / transmitter trigger level */
|
|
val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
|
|
val |= TXTL << UFCR_TXTL_SHF | RXTL;
|
|
writel(val, sport->port.membase + UFCR);
|
|
return 0;
|
|
}
|
|
|
|
/* half the RX buffer size */
|
|
#define CTSTL 16
|
|
|
|
static int imx_startup(struct uart_port *port)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
int retval;
|
|
unsigned long flags, temp;
|
|
|
|
imx_setup_ufcr(sport, 0);
|
|
|
|
/* disable the DREN bit (Data Ready interrupt enable) before
|
|
* requesting IRQs
|
|
*/
|
|
temp = readl(sport->port.membase + UCR4);
|
|
|
|
if (USE_IRDA(sport))
|
|
temp |= UCR4_IRSC;
|
|
|
|
/* set the trigger level for CTS */
|
|
temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
|
|
temp |= CTSTL << UCR4_CTSTL_SHF;
|
|
|
|
writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
|
|
|
|
if (USE_IRDA(sport)) {
|
|
/* reset fifo's and state machines */
|
|
int i = 100;
|
|
temp = readl(sport->port.membase + UCR2);
|
|
temp &= ~UCR2_SRST;
|
|
writel(temp, sport->port.membase + UCR2);
|
|
while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
|
|
(--i > 0)) {
|
|
udelay(1);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Allocate the IRQ(s) i.MX1 has three interrupts whereas later
|
|
* chips only have one interrupt.
|
|
*/
|
|
if (sport->txirq > 0) {
|
|
retval = request_irq(sport->rxirq, imx_rxint, 0,
|
|
DRIVER_NAME, sport);
|
|
if (retval)
|
|
goto error_out1;
|
|
|
|
retval = request_irq(sport->txirq, imx_txint, 0,
|
|
DRIVER_NAME, sport);
|
|
if (retval)
|
|
goto error_out2;
|
|
|
|
/* do not use RTS IRQ on IrDA */
|
|
if (!USE_IRDA(sport)) {
|
|
retval = request_irq(sport->rtsirq, imx_rtsint, 0,
|
|
DRIVER_NAME, sport);
|
|
if (retval)
|
|
goto error_out3;
|
|
}
|
|
} else {
|
|
retval = request_irq(sport->port.irq, imx_int, 0,
|
|
DRIVER_NAME, sport);
|
|
if (retval) {
|
|
free_irq(sport->port.irq, sport);
|
|
goto error_out1;
|
|
}
|
|
}
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
/*
|
|
* Finally, clear and enable interrupts
|
|
*/
|
|
writel(USR1_RTSD, sport->port.membase + USR1);
|
|
|
|
temp = readl(sport->port.membase + UCR1);
|
|
temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
|
|
|
|
if (USE_IRDA(sport)) {
|
|
temp |= UCR1_IREN;
|
|
temp &= ~(UCR1_RTSDEN);
|
|
}
|
|
|
|
writel(temp, sport->port.membase + UCR1);
|
|
|
|
temp = readl(sport->port.membase + UCR2);
|
|
temp |= (UCR2_RXEN | UCR2_TXEN);
|
|
writel(temp, sport->port.membase + UCR2);
|
|
|
|
if (USE_IRDA(sport)) {
|
|
/* clear RX-FIFO */
|
|
int i = 64;
|
|
while ((--i > 0) &&
|
|
(readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
|
|
barrier();
|
|
}
|
|
}
|
|
|
|
if (is_imx21_uart(sport)) {
|
|
temp = readl(sport->port.membase + UCR3);
|
|
temp |= IMX21_UCR3_RXDMUXSEL;
|
|
writel(temp, sport->port.membase + UCR3);
|
|
}
|
|
|
|
if (USE_IRDA(sport)) {
|
|
temp = readl(sport->port.membase + UCR4);
|
|
if (sport->irda_inv_rx)
|
|
temp |= UCR4_INVR;
|
|
else
|
|
temp &= ~(UCR4_INVR);
|
|
writel(temp | UCR4_DREN, sport->port.membase + UCR4);
|
|
|
|
temp = readl(sport->port.membase + UCR3);
|
|
if (sport->irda_inv_tx)
|
|
temp |= UCR3_INVT;
|
|
else
|
|
temp &= ~(UCR3_INVT);
|
|
writel(temp, sport->port.membase + UCR3);
|
|
}
|
|
|
|
/*
|
|
* Enable modem status interrupts
|
|
*/
|
|
imx_enable_ms(&sport->port);
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
|
|
if (USE_IRDA(sport)) {
|
|
struct imxuart_platform_data *pdata;
|
|
pdata = sport->port.dev->platform_data;
|
|
sport->irda_inv_rx = pdata->irda_inv_rx;
|
|
sport->irda_inv_tx = pdata->irda_inv_tx;
|
|
sport->trcv_delay = pdata->transceiver_delay;
|
|
if (pdata->irda_enable)
|
|
pdata->irda_enable(1);
|
|
}
|
|
|
|
return 0;
|
|
|
|
error_out3:
|
|
if (sport->txirq)
|
|
free_irq(sport->txirq, sport);
|
|
error_out2:
|
|
if (sport->rxirq)
|
|
free_irq(sport->rxirq, sport);
|
|
error_out1:
|
|
return retval;
|
|
}
|
|
|
|
static void imx_shutdown(struct uart_port *port)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
unsigned long temp;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
temp = readl(sport->port.membase + UCR2);
|
|
temp &= ~(UCR2_TXEN);
|
|
writel(temp, sport->port.membase + UCR2);
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
|
|
if (USE_IRDA(sport)) {
|
|
struct imxuart_platform_data *pdata;
|
|
pdata = sport->port.dev->platform_data;
|
|
if (pdata->irda_enable)
|
|
pdata->irda_enable(0);
|
|
}
|
|
|
|
/*
|
|
* Stop our timer.
|
|
*/
|
|
del_timer_sync(&sport->timer);
|
|
|
|
/*
|
|
* Free the interrupts
|
|
*/
|
|
if (sport->txirq > 0) {
|
|
if (!USE_IRDA(sport))
|
|
free_irq(sport->rtsirq, sport);
|
|
free_irq(sport->txirq, sport);
|
|
free_irq(sport->rxirq, sport);
|
|
} else
|
|
free_irq(sport->port.irq, sport);
|
|
|
|
/*
|
|
* Disable all interrupts, port and break condition.
|
|
*/
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
temp = readl(sport->port.membase + UCR1);
|
|
temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
|
|
if (USE_IRDA(sport))
|
|
temp &= ~(UCR1_IREN);
|
|
|
|
writel(temp, sport->port.membase + UCR1);
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
}
|
|
|
|
static void
|
|
imx_set_termios(struct uart_port *port, struct ktermios *termios,
|
|
struct ktermios *old)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
unsigned long flags;
|
|
unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
|
|
unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
|
|
unsigned int div, ufcr;
|
|
unsigned long num, denom;
|
|
uint64_t tdiv64;
|
|
|
|
/*
|
|
* If we don't support modem control lines, don't allow
|
|
* these to be set.
|
|
*/
|
|
if (0) {
|
|
termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
|
|
termios->c_cflag |= CLOCAL;
|
|
}
|
|
|
|
/*
|
|
* We only support CS7 and CS8.
|
|
*/
|
|
while ((termios->c_cflag & CSIZE) != CS7 &&
|
|
(termios->c_cflag & CSIZE) != CS8) {
|
|
termios->c_cflag &= ~CSIZE;
|
|
termios->c_cflag |= old_csize;
|
|
old_csize = CS8;
|
|
}
|
|
|
|
if ((termios->c_cflag & CSIZE) == CS8)
|
|
ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
|
|
else
|
|
ucr2 = UCR2_SRST | UCR2_IRTS;
|
|
|
|
if (termios->c_cflag & CRTSCTS) {
|
|
if (sport->have_rtscts) {
|
|
ucr2 &= ~UCR2_IRTS;
|
|
ucr2 |= UCR2_CTSC;
|
|
} else {
|
|
termios->c_cflag &= ~CRTSCTS;
|
|
}
|
|
}
|
|
|
|
if (termios->c_cflag & CSTOPB)
|
|
ucr2 |= UCR2_STPB;
|
|
if (termios->c_cflag & PARENB) {
|
|
ucr2 |= UCR2_PREN;
|
|
if (termios->c_cflag & PARODD)
|
|
ucr2 |= UCR2_PROE;
|
|
}
|
|
|
|
del_timer_sync(&sport->timer);
|
|
|
|
/*
|
|
* Ask the core to calculate the divisor for us.
|
|
*/
|
|
baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
|
|
quot = uart_get_divisor(port, baud);
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
|
|
sport->port.read_status_mask = 0;
|
|
if (termios->c_iflag & INPCK)
|
|
sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
sport->port.read_status_mask |= URXD_BRK;
|
|
|
|
/*
|
|
* Characters to ignore
|
|
*/
|
|
sport->port.ignore_status_mask = 0;
|
|
if (termios->c_iflag & IGNPAR)
|
|
sport->port.ignore_status_mask |= URXD_PRERR;
|
|
if (termios->c_iflag & IGNBRK) {
|
|
sport->port.ignore_status_mask |= URXD_BRK;
|
|
/*
|
|
* If we're ignoring parity and break indicators,
|
|
* ignore overruns too (for real raw support).
|
|
*/
|
|
if (termios->c_iflag & IGNPAR)
|
|
sport->port.ignore_status_mask |= URXD_OVRRUN;
|
|
}
|
|
|
|
/*
|
|
* Update the per-port timeout.
|
|
*/
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
/*
|
|
* disable interrupts and drain transmitter
|
|
*/
|
|
old_ucr1 = readl(sport->port.membase + UCR1);
|
|
writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
|
|
sport->port.membase + UCR1);
|
|
|
|
while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
|
|
barrier();
|
|
|
|
/* then, disable everything */
|
|
old_txrxen = readl(sport->port.membase + UCR2);
|
|
writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
|
|
sport->port.membase + UCR2);
|
|
old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
|
|
|
|
if (USE_IRDA(sport)) {
|
|
/*
|
|
* use maximum available submodule frequency to
|
|
* avoid missing short pulses due to low sampling rate
|
|
*/
|
|
div = 1;
|
|
} else {
|
|
div = sport->port.uartclk / (baud * 16);
|
|
if (div > 7)
|
|
div = 7;
|
|
if (!div)
|
|
div = 1;
|
|
}
|
|
|
|
rational_best_approximation(16 * div * baud, sport->port.uartclk,
|
|
1 << 16, 1 << 16, &num, &denom);
|
|
|
|
tdiv64 = sport->port.uartclk;
|
|
tdiv64 *= num;
|
|
do_div(tdiv64, denom * 16 * div);
|
|
tty_termios_encode_baud_rate(termios,
|
|
(speed_t)tdiv64, (speed_t)tdiv64);
|
|
|
|
num -= 1;
|
|
denom -= 1;
|
|
|
|
ufcr = readl(sport->port.membase + UFCR);
|
|
ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
|
|
writel(ufcr, sport->port.membase + UFCR);
|
|
|
|
writel(num, sport->port.membase + UBIR);
|
|
writel(denom, sport->port.membase + UBMR);
|
|
|
|
if (is_imx21_uart(sport))
|
|
writel(sport->port.uartclk / div / 1000,
|
|
sport->port.membase + IMX21_ONEMS);
|
|
|
|
writel(old_ucr1, sport->port.membase + UCR1);
|
|
|
|
/* set the parity, stop bits and data size */
|
|
writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
|
|
|
|
if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
|
|
imx_enable_ms(&sport->port);
|
|
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
}
|
|
|
|
static const char *imx_type(struct uart_port *port)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
|
|
return sport->port.type == PORT_IMX ? "IMX" : NULL;
|
|
}
|
|
|
|
/*
|
|
* Release the memory region(s) being used by 'port'.
|
|
*/
|
|
static void imx_release_port(struct uart_port *port)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(port->dev);
|
|
struct resource *mmres;
|
|
|
|
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(mmres->start, resource_size(mmres));
|
|
}
|
|
|
|
/*
|
|
* Request the memory region(s) being used by 'port'.
|
|
*/
|
|
static int imx_request_port(struct uart_port *port)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(port->dev);
|
|
struct resource *mmres;
|
|
void *ret;
|
|
|
|
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mmres)
|
|
return -ENODEV;
|
|
|
|
ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
|
|
|
|
return ret ? 0 : -EBUSY;
|
|
}
|
|
|
|
/*
|
|
* Configure/autoconfigure the port.
|
|
*/
|
|
static void imx_config_port(struct uart_port *port, int flags)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
|
|
if (flags & UART_CONFIG_TYPE &&
|
|
imx_request_port(&sport->port) == 0)
|
|
sport->port.type = PORT_IMX;
|
|
}
|
|
|
|
/*
|
|
* Verify the new serial_struct (for TIOCSSERIAL).
|
|
* The only change we allow are to the flags and type, and
|
|
* even then only between PORT_IMX and PORT_UNKNOWN
|
|
*/
|
|
static int
|
|
imx_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
int ret = 0;
|
|
|
|
if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
|
|
ret = -EINVAL;
|
|
if (sport->port.irq != ser->irq)
|
|
ret = -EINVAL;
|
|
if (ser->io_type != UPIO_MEM)
|
|
ret = -EINVAL;
|
|
if (sport->port.uartclk / 16 != ser->baud_base)
|
|
ret = -EINVAL;
|
|
if ((void *)sport->port.mapbase != ser->iomem_base)
|
|
ret = -EINVAL;
|
|
if (sport->port.iobase != ser->port)
|
|
ret = -EINVAL;
|
|
if (ser->hub6 != 0)
|
|
ret = -EINVAL;
|
|
return ret;
|
|
}
|
|
|
|
#if defined(CONFIG_CONSOLE_POLL)
|
|
/*
|
|
* Save and restore functions for UCR1, UCR2 and UCR3 registers
|
|
*/
|
|
static void imx_port_ucrs_save(struct uart_port *port,
|
|
struct imx_port_ucrs *ucr)
|
|
{
|
|
/* save control registers */
|
|
ucr->ucr1 = readl(port->membase + UCR1);
|
|
ucr->ucr2 = readl(port->membase + UCR2);
|
|
ucr->ucr3 = readl(port->membase + UCR3);
|
|
}
|
|
|
|
static void imx_port_ucrs_restore(struct uart_port *port,
|
|
struct imx_port_ucrs *ucr)
|
|
{
|
|
/* restore control registers */
|
|
writel(ucr->ucr1, port->membase + UCR1);
|
|
writel(ucr->ucr2, port->membase + UCR2);
|
|
writel(ucr->ucr3, port->membase + UCR3);
|
|
}
|
|
|
|
static int imx_poll_get_char(struct uart_port *port)
|
|
{
|
|
struct imx_port_ucrs old_ucr;
|
|
unsigned int status;
|
|
unsigned char c;
|
|
|
|
/* save control registers */
|
|
imx_port_ucrs_save(port, &old_ucr);
|
|
|
|
/* disable interrupts */
|
|
writel(UCR1_UARTEN, port->membase + UCR1);
|
|
writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
|
|
port->membase + UCR2);
|
|
writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
|
|
port->membase + UCR3);
|
|
|
|
/* poll */
|
|
do {
|
|
status = readl(port->membase + USR2);
|
|
} while (~status & USR2_RDR);
|
|
|
|
/* read */
|
|
c = readl(port->membase + URXD0);
|
|
|
|
/* restore control registers */
|
|
imx_port_ucrs_restore(port, &old_ucr);
|
|
|
|
return c;
|
|
}
|
|
|
|
static void imx_poll_put_char(struct uart_port *port, unsigned char c)
|
|
{
|
|
struct imx_port_ucrs old_ucr;
|
|
unsigned int status;
|
|
|
|
/* save control registers */
|
|
imx_port_ucrs_save(port, &old_ucr);
|
|
|
|
/* disable interrupts */
|
|
writel(UCR1_UARTEN, port->membase + UCR1);
|
|
writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
|
|
port->membase + UCR2);
|
|
writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
|
|
port->membase + UCR3);
|
|
|
|
/* drain */
|
|
do {
|
|
status = readl(port->membase + USR1);
|
|
} while (~status & USR1_TRDY);
|
|
|
|
/* write */
|
|
writel(c, port->membase + URTX0);
|
|
|
|
/* flush */
|
|
do {
|
|
status = readl(port->membase + USR2);
|
|
} while (~status & USR2_TXDC);
|
|
|
|
/* restore control registers */
|
|
imx_port_ucrs_restore(port, &old_ucr);
|
|
}
|
|
#endif
|
|
|
|
static struct uart_ops imx_pops = {
|
|
.tx_empty = imx_tx_empty,
|
|
.set_mctrl = imx_set_mctrl,
|
|
.get_mctrl = imx_get_mctrl,
|
|
.stop_tx = imx_stop_tx,
|
|
.start_tx = imx_start_tx,
|
|
.stop_rx = imx_stop_rx,
|
|
.enable_ms = imx_enable_ms,
|
|
.break_ctl = imx_break_ctl,
|
|
.startup = imx_startup,
|
|
.shutdown = imx_shutdown,
|
|
.set_termios = imx_set_termios,
|
|
.type = imx_type,
|
|
.release_port = imx_release_port,
|
|
.request_port = imx_request_port,
|
|
.config_port = imx_config_port,
|
|
.verify_port = imx_verify_port,
|
|
#if defined(CONFIG_CONSOLE_POLL)
|
|
.poll_get_char = imx_poll_get_char,
|
|
.poll_put_char = imx_poll_put_char,
|
|
#endif
|
|
};
|
|
|
|
static struct imx_port *imx_ports[UART_NR];
|
|
|
|
#ifdef CONFIG_SERIAL_IMX_CONSOLE
|
|
static void imx_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
struct imx_port *sport = (struct imx_port *)port;
|
|
|
|
while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
|
|
barrier();
|
|
|
|
writel(ch, sport->port.membase + URTX0);
|
|
}
|
|
|
|
/*
|
|
* Interrupts are disabled on entering
|
|
*/
|
|
static void
|
|
imx_console_write(struct console *co, const char *s, unsigned int count)
|
|
{
|
|
struct imx_port *sport = imx_ports[co->index];
|
|
struct imx_port_ucrs old_ucr;
|
|
unsigned int ucr1;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&sport->port.lock, flags);
|
|
|
|
/*
|
|
* First, save UCR1/2/3 and then disable interrupts
|
|
*/
|
|
imx_port_ucrs_save(&sport->port, &old_ucr);
|
|
ucr1 = old_ucr.ucr1;
|
|
|
|
if (is_imx1_uart(sport))
|
|
ucr1 |= IMX1_UCR1_UARTCLKEN;
|
|
ucr1 |= UCR1_UARTEN;
|
|
ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
|
|
|
|
writel(ucr1, sport->port.membase + UCR1);
|
|
|
|
writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
|
|
|
|
uart_console_write(&sport->port, s, count, imx_console_putchar);
|
|
|
|
/*
|
|
* Finally, wait for transmitter to become empty
|
|
* and restore UCR1/2/3
|
|
*/
|
|
while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
|
|
|
|
imx_port_ucrs_restore(&sport->port, &old_ucr);
|
|
|
|
spin_unlock_irqrestore(&sport->port.lock, flags);
|
|
}
|
|
|
|
/*
|
|
* If the port was already initialised (eg, by a boot loader),
|
|
* try to determine the current setup.
|
|
*/
|
|
static void __init
|
|
imx_console_get_options(struct imx_port *sport, int *baud,
|
|
int *parity, int *bits)
|
|
{
|
|
|
|
if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
|
|
/* ok, the port was enabled */
|
|
unsigned int ucr2, ubir, ubmr, uartclk;
|
|
unsigned int baud_raw;
|
|
unsigned int ucfr_rfdiv;
|
|
|
|
ucr2 = readl(sport->port.membase + UCR2);
|
|
|
|
*parity = 'n';
|
|
if (ucr2 & UCR2_PREN) {
|
|
if (ucr2 & UCR2_PROE)
|
|
*parity = 'o';
|
|
else
|
|
*parity = 'e';
|
|
}
|
|
|
|
if (ucr2 & UCR2_WS)
|
|
*bits = 8;
|
|
else
|
|
*bits = 7;
|
|
|
|
ubir = readl(sport->port.membase + UBIR) & 0xffff;
|
|
ubmr = readl(sport->port.membase + UBMR) & 0xffff;
|
|
|
|
ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
|
|
if (ucfr_rfdiv == 6)
|
|
ucfr_rfdiv = 7;
|
|
else
|
|
ucfr_rfdiv = 6 - ucfr_rfdiv;
|
|
|
|
uartclk = clk_get_rate(sport->clk_per);
|
|
uartclk /= ucfr_rfdiv;
|
|
|
|
{ /*
|
|
* The next code provides exact computation of
|
|
* baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
|
|
* without need of float support or long long division,
|
|
* which would be required to prevent 32bit arithmetic overflow
|
|
*/
|
|
unsigned int mul = ubir + 1;
|
|
unsigned int div = 16 * (ubmr + 1);
|
|
unsigned int rem = uartclk % div;
|
|
|
|
baud_raw = (uartclk / div) * mul;
|
|
baud_raw += (rem * mul + div / 2) / div;
|
|
*baud = (baud_raw + 50) / 100 * 100;
|
|
}
|
|
|
|
if (*baud != baud_raw)
|
|
pr_info("Console IMX rounded baud rate from %d to %d\n",
|
|
baud_raw, *baud);
|
|
}
|
|
}
|
|
|
|
static int __init
|
|
imx_console_setup(struct console *co, char *options)
|
|
{
|
|
struct imx_port *sport;
|
|
int baud = 9600;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
/*
|
|
* Check whether an invalid uart number has been specified, and
|
|
* if so, search for the first available port that does have
|
|
* console support.
|
|
*/
|
|
if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
|
|
co->index = 0;
|
|
sport = imx_ports[co->index];
|
|
if (sport == NULL)
|
|
return -ENODEV;
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
else
|
|
imx_console_get_options(sport, &baud, &parity, &bits);
|
|
|
|
imx_setup_ufcr(sport, 0);
|
|
|
|
return uart_set_options(&sport->port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver imx_reg;
|
|
static struct console imx_console = {
|
|
.name = DEV_NAME,
|
|
.write = imx_console_write,
|
|
.device = uart_console_device,
|
|
.setup = imx_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &imx_reg,
|
|
};
|
|
|
|
#define IMX_CONSOLE &imx_console
|
|
#else
|
|
#define IMX_CONSOLE NULL
|
|
#endif
|
|
|
|
static struct uart_driver imx_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = DRIVER_NAME,
|
|
.dev_name = DEV_NAME,
|
|
.major = SERIAL_IMX_MAJOR,
|
|
.minor = MINOR_START,
|
|
.nr = ARRAY_SIZE(imx_ports),
|
|
.cons = IMX_CONSOLE,
|
|
};
|
|
|
|
static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct imx_port *sport = platform_get_drvdata(dev);
|
|
unsigned int val;
|
|
|
|
/* enable wakeup from i.MX UART */
|
|
val = readl(sport->port.membase + UCR3);
|
|
val |= UCR3_AWAKEN;
|
|
writel(val, sport->port.membase + UCR3);
|
|
|
|
uart_suspend_port(&imx_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int serial_imx_resume(struct platform_device *dev)
|
|
{
|
|
struct imx_port *sport = platform_get_drvdata(dev);
|
|
unsigned int val;
|
|
|
|
/* disable wakeup from i.MX UART */
|
|
val = readl(sport->port.membase + UCR3);
|
|
val &= ~UCR3_AWAKEN;
|
|
writel(val, sport->port.membase + UCR3);
|
|
|
|
uart_resume_port(&imx_reg, &sport->port);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
/*
|
|
* This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
|
|
* could successfully get all information from dt or a negative errno.
|
|
*/
|
|
static int serial_imx_probe_dt(struct imx_port *sport,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
const struct of_device_id *of_id =
|
|
of_match_device(imx_uart_dt_ids, &pdev->dev);
|
|
int ret;
|
|
|
|
if (!np)
|
|
/* no device tree device */
|
|
return 1;
|
|
|
|
ret = of_alias_get_id(np, "serial");
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
|
|
return ret;
|
|
}
|
|
sport->port.line = ret;
|
|
|
|
if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
|
|
sport->have_rtscts = 1;
|
|
|
|
if (of_get_property(np, "fsl,irda-mode", NULL))
|
|
sport->use_irda = 1;
|
|
|
|
sport->devdata = of_id->data;
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static inline int serial_imx_probe_dt(struct imx_port *sport,
|
|
struct platform_device *pdev)
|
|
{
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
static void serial_imx_probe_pdata(struct imx_port *sport,
|
|
struct platform_device *pdev)
|
|
{
|
|
struct imxuart_platform_data *pdata = pdev->dev.platform_data;
|
|
|
|
sport->port.line = pdev->id;
|
|
sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
|
|
|
|
if (!pdata)
|
|
return;
|
|
|
|
if (pdata->flags & IMXUART_HAVE_RTSCTS)
|
|
sport->have_rtscts = 1;
|
|
|
|
if (pdata->flags & IMXUART_IRDA)
|
|
sport->use_irda = 1;
|
|
}
|
|
|
|
static int serial_imx_probe(struct platform_device *pdev)
|
|
{
|
|
struct imx_port *sport;
|
|
struct imxuart_platform_data *pdata;
|
|
void __iomem *base;
|
|
int ret = 0;
|
|
struct resource *res;
|
|
struct pinctrl *pinctrl;
|
|
|
|
sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
|
|
if (!sport)
|
|
return -ENOMEM;
|
|
|
|
ret = serial_imx_probe_dt(sport, pdev);
|
|
if (ret > 0)
|
|
serial_imx_probe_pdata(sport, pdev);
|
|
else if (ret < 0)
|
|
return ret;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -ENODEV;
|
|
|
|
base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
|
|
if (!base)
|
|
return -ENOMEM;
|
|
|
|
sport->port.dev = &pdev->dev;
|
|
sport->port.mapbase = res->start;
|
|
sport->port.membase = base;
|
|
sport->port.type = PORT_IMX,
|
|
sport->port.iotype = UPIO_MEM;
|
|
sport->port.irq = platform_get_irq(pdev, 0);
|
|
sport->rxirq = platform_get_irq(pdev, 0);
|
|
sport->txirq = platform_get_irq(pdev, 1);
|
|
sport->rtsirq = platform_get_irq(pdev, 2);
|
|
sport->port.fifosize = 32;
|
|
sport->port.ops = &imx_pops;
|
|
sport->port.flags = UPF_BOOT_AUTOCONF;
|
|
init_timer(&sport->timer);
|
|
sport->timer.function = imx_timeout;
|
|
sport->timer.data = (unsigned long)sport;
|
|
|
|
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
|
if (IS_ERR(pinctrl)) {
|
|
ret = PTR_ERR(pinctrl);
|
|
dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
|
|
if (IS_ERR(sport->clk_ipg)) {
|
|
ret = PTR_ERR(sport->clk_ipg);
|
|
dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
sport->clk_per = devm_clk_get(&pdev->dev, "per");
|
|
if (IS_ERR(sport->clk_per)) {
|
|
ret = PTR_ERR(sport->clk_per);
|
|
dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
clk_prepare_enable(sport->clk_per);
|
|
clk_prepare_enable(sport->clk_ipg);
|
|
|
|
sport->port.uartclk = clk_get_rate(sport->clk_per);
|
|
|
|
imx_ports[sport->port.line] = sport;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (pdata && pdata->init) {
|
|
ret = pdata->init(pdev);
|
|
if (ret)
|
|
goto clkput;
|
|
}
|
|
|
|
ret = uart_add_one_port(&imx_reg, &sport->port);
|
|
if (ret)
|
|
goto deinit;
|
|
platform_set_drvdata(pdev, sport);
|
|
|
|
return 0;
|
|
deinit:
|
|
if (pdata && pdata->exit)
|
|
pdata->exit(pdev);
|
|
clkput:
|
|
clk_disable_unprepare(sport->clk_per);
|
|
clk_disable_unprepare(sport->clk_ipg);
|
|
return ret;
|
|
}
|
|
|
|
static int serial_imx_remove(struct platform_device *pdev)
|
|
{
|
|
struct imxuart_platform_data *pdata;
|
|
struct imx_port *sport = platform_get_drvdata(pdev);
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
uart_remove_one_port(&imx_reg, &sport->port);
|
|
|
|
clk_disable_unprepare(sport->clk_per);
|
|
clk_disable_unprepare(sport->clk_ipg);
|
|
|
|
if (pdata && pdata->exit)
|
|
pdata->exit(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver serial_imx_driver = {
|
|
.probe = serial_imx_probe,
|
|
.remove = serial_imx_remove,
|
|
|
|
.suspend = serial_imx_suspend,
|
|
.resume = serial_imx_resume,
|
|
.id_table = imx_uart_devtype,
|
|
.driver = {
|
|
.name = "imx-uart",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = imx_uart_dt_ids,
|
|
},
|
|
};
|
|
|
|
static int __init imx_serial_init(void)
|
|
{
|
|
int ret;
|
|
|
|
pr_info("Serial: IMX driver\n");
|
|
|
|
ret = uart_register_driver(&imx_reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&serial_imx_driver);
|
|
if (ret != 0)
|
|
uart_unregister_driver(&imx_reg);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit imx_serial_exit(void)
|
|
{
|
|
platform_driver_unregister(&serial_imx_driver);
|
|
uart_unregister_driver(&imx_reg);
|
|
}
|
|
|
|
module_init(imx_serial_init);
|
|
module_exit(imx_serial_exit);
|
|
|
|
MODULE_AUTHOR("Sascha Hauer");
|
|
MODULE_DESCRIPTION("IMX generic serial port driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:imx-uart");
|