371 lines
7.2 KiB
ArmAsm
371 lines
7.2 KiB
ArmAsm
/*
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* arch/arm/mach-at91/pm_slow_clock.S
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*
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* Copyright (C) 2006 Savin Zlobec
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*
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* AT91SAM9 support:
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* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/clk/at91_pmc.h>
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#include "pm.h"
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#include "generated/at91_pm_data-offsets.h"
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#define SRAMC_SELF_FRESH_ACTIVE 0x01
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#define SRAMC_SELF_FRESH_EXIT 0x00
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pmc .req r0
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tmp1 .req r4
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tmp2 .req r5
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/*
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* Wait until master clock is ready (after switching master clock source)
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*/
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.macro wait_mckrdy
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1: ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_MCKRDY
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beq 1b
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.endm
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/*
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* Wait until master oscillator has stabilized.
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*/
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.macro wait_moscrdy
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1: ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_MOSCS
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beq 1b
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.endm
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/*
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* Wait until PLLA has locked.
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*/
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.macro wait_pllalock
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1: ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_LOCKA
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beq 1b
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.endm
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/*
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* Put the processor to enter the idle state
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*/
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.macro at91_cpu_idle
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#if defined(CONFIG_CPU_V7)
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mov tmp1, #AT91_PMC_PCK
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str tmp1, [pmc, #AT91_PMC_SCDR]
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dsb
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wfi @ Wait For Interrupt
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#else
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mcr p15, 0, tmp1, c7, c0, 4
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#endif
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.endm
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.text
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.arm
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/*
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* void at91_suspend_sram_fn(struct at91_pm_data*)
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* @input param:
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* @r0: base address of struct at91_pm_data
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*/
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/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
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.align 3
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ENTRY(at91_pm_suspend_in_sram)
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/* Save registers on stack */
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stmfd sp!, {r4 - r12, lr}
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/* Drain write buffer */
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mov tmp1, #0
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mcr p15, 0, tmp1, c7, c10, 4
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ldr tmp1, [r0, #PM_DATA_PMC]
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str tmp1, .pmc_base
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ldr tmp1, [r0, #PM_DATA_RAMC0]
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str tmp1, .sramc_base
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ldr tmp1, [r0, #PM_DATA_RAMC1]
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str tmp1, .sramc1_base
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ldr tmp1, [r0, #PM_DATA_MEMCTRL]
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str tmp1, .memtype
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ldr tmp1, [r0, #PM_DATA_MODE]
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str tmp1, .pm_mode
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/* Both ldrne below are here to preload their address in the TLB */
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ldr tmp1, [r0, #PM_DATA_SHDWC]
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str tmp1, .shdwc
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0]
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ldr tmp1, [r0, #PM_DATA_SFRBU]
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str tmp1, .sfr
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cmp tmp1, #0
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ldrne tmp2, [tmp1, #0x10]
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/* Active the self-refresh mode */
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mov r0, #SRAMC_SELF_FRESH_ACTIVE
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bl at91_sramc_self_refresh
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ldr r0, .pm_mode
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cmp r0, #AT91_PM_SLOW_CLOCK
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beq slow_clock
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cmp r0, #AT91_PM_BACKUP
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beq backup_mode
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/* Wait for interrupt */
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ldr pmc, .pmc_base
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at91_cpu_idle
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b exit_suspend
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slow_clock:
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bl at91_slowck_mode
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b exit_suspend
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backup_mode:
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bl at91_backup_mode
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b exit_suspend
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exit_suspend:
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/* Exit the self-refresh mode */
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mov r0, #SRAMC_SELF_FRESH_EXIT
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bl at91_sramc_self_refresh
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/* Restore registers, and return */
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ldmfd sp!, {r4 - r12, pc}
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ENDPROC(at91_pm_suspend_in_sram)
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ENTRY(at91_backup_mode)
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/*BUMEN*/
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ldr r0, .sfr
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mov tmp1, #0x1
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str tmp1, [r0, #0x10]
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/* Shutdown */
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ldr r0, .shdwc
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mov tmp1, #0xA5000000
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add tmp1, tmp1, #0x1
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str tmp1, [r0, #0]
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ENDPROC(at91_backup_mode)
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ENTRY(at91_slowck_mode)
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ldr pmc, .pmc_base
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/* Save Master clock setting */
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ldr tmp1, [pmc, #AT91_PMC_MCKR]
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str tmp1, .saved_mckr
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/*
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* Set the Master clock source to slow clock
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*/
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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/* Save PLLA setting and disable it */
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ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
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str tmp1, .saved_pllar
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mov tmp1, #AT91_PMC_PLLCOUNT
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orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
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str tmp1, [pmc, #AT91_CKGR_PLLAR]
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/* Turn off the main oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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bic tmp1, tmp1, #AT91_PMC_MOSCEN
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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/* Wait for interrupt */
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at91_cpu_idle
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/* Turn on the main oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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orr tmp1, tmp1, #AT91_PMC_MOSCEN
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orr tmp1, tmp1, #AT91_PMC_KEY
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str tmp1, [pmc, #AT91_CKGR_MOR]
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wait_moscrdy
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/* Restore PLLA setting */
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ldr tmp1, .saved_pllar
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str tmp1, [pmc, #AT91_CKGR_PLLAR]
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tst tmp1, #(AT91_PMC_MUL & 0xff0000)
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bne 3f
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tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
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beq 4f
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3:
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wait_pllalock
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4:
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/*
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* Restore master clock setting
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*/
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ldr tmp1, .saved_mckr
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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mov pc, lr
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ENDPROC(at91_slowck_mode)
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/*
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* void at91_sramc_self_refresh(unsigned int is_active)
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*
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* @input param:
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* @r0: 1 - active self-refresh mode
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* 0 - exit self-refresh mode
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* register usage:
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* @r1: memory type
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* @r2: base address of the sram controller
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*/
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ENTRY(at91_sramc_self_refresh)
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ldr r1, .memtype
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ldr r2, .sramc_base
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cmp r1, #AT91_MEMCTRL_MC
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bne ddrc_sf
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/*
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* at91rm9200 Memory controller
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*/
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/*
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* For exiting the self-refresh mode, do nothing,
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* automatically exit the self-refresh mode.
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*/
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq exit_sramc_sf
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/* Active SDRAM self-refresh mode */
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mov r3, #1
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str r3, [r2, #AT91_MC_SDRAMC_SRR]
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b exit_sramc_sf
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ddrc_sf:
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cmp r1, #AT91_MEMCTRL_DDRSDR
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bne sdramc_sf
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/*
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* DDR Memory controller
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*/
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq ddrc_exit_sf
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/* LPDDR1 --> force DDR2 mode during self-refresh */
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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str r3, .saved_sam9_mdr
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bic r3, r3, #~AT91_DDRSDRC_MD
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cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq r3, [r2, #AT91_DDRSDRC_MDR]
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biceq r3, r3, #AT91_DDRSDRC_MD
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orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
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streq r3, [r2, #AT91_DDRSDRC_MDR]
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/* Active DDRC self-refresh mode */
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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str r3, .saved_sam9_lpr
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bic r3, r3, #AT91_DDRSDRC_LPCB
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orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR]
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/* If using the 2nd ddr controller */
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ldr r2, .sramc1_base
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cmp r2, #0
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beq no_2nd_ddrc
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ldr r3, [r2, #AT91_DDRSDRC_MDR]
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str r3, .saved_sam9_mdr1
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bic r3, r3, #~AT91_DDRSDRC_MD
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cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
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ldreq r3, [r2, #AT91_DDRSDRC_MDR]
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biceq r3, r3, #AT91_DDRSDRC_MD
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orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
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streq r3, [r2, #AT91_DDRSDRC_MDR]
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/* Active DDRC self-refresh mode */
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ldr r3, [r2, #AT91_DDRSDRC_LPR]
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str r3, .saved_sam9_lpr1
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bic r3, r3, #AT91_DDRSDRC_LPCB
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orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_DDRSDRC_LPR]
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no_2nd_ddrc:
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b exit_sramc_sf
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ddrc_exit_sf:
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/* Restore MDR in case of LPDDR1 */
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ldr r3, .saved_sam9_mdr
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str r3, [r2, #AT91_DDRSDRC_MDR]
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/* Restore LPR on AT91 with DDRAM */
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_DDRSDRC_LPR]
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/* If using the 2nd ddr controller */
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ldr r2, .sramc1_base
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cmp r2, #0
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ldrne r3, .saved_sam9_mdr1
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strne r3, [r2, #AT91_DDRSDRC_MDR]
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ldrne r3, .saved_sam9_lpr1
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strne r3, [r2, #AT91_DDRSDRC_LPR]
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b exit_sramc_sf
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/*
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* SDRAMC Memory controller
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*/
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sdramc_sf:
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tst r0, #SRAMC_SELF_FRESH_ACTIVE
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beq sdramc_exit_sf
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/* Active SDRAMC self-refresh mode */
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ldr r3, [r2, #AT91_SDRAMC_LPR]
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str r3, .saved_sam9_lpr
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bic r3, r3, #AT91_SDRAMC_LPCB
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orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str r3, [r2, #AT91_SDRAMC_LPR]
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sdramc_exit_sf:
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ldr r3, .saved_sam9_lpr
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str r3, [r2, #AT91_SDRAMC_LPR]
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exit_sramc_sf:
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mov pc, lr
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ENDPROC(at91_sramc_self_refresh)
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.pmc_base:
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.word 0
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.sramc_base:
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.word 0
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.sramc1_base:
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.word 0
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.shdwc:
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.word 0
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.sfr:
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.word 0
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.memtype:
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.word 0
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.pm_mode:
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.word 0
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.saved_mckr:
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.word 0
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.saved_pllar:
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.word 0
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.saved_sam9_lpr:
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.word 0
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.saved_sam9_lpr1:
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.word 0
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.saved_sam9_mdr:
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.word 0
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.saved_sam9_mdr1:
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.word 0
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ENTRY(at91_pm_suspend_in_sram_sz)
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.word .-at91_pm_suspend_in_sram
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