679 lines
15 KiB
C
679 lines
15 KiB
C
/*
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* Driver for NEC VR4100 series General-purpose I/O Unit.
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
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* Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/errno.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/vr41xx/giu.h>
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#include <asm/vr41xx/irq.h>
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#include <asm/vr41xx/vr41xx.h>
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MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
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MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
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MODULE_LICENSE("GPL");
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static int major; /* default is dynamic major device number */
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module_param(major, int, 0);
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MODULE_PARM_DESC(major, "Major device number");
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#define GIUIOSELL 0x00
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#define GIUIOSELH 0x02
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#define GIUPIODL 0x04
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#define GIUPIODH 0x06
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#define GIUINTSTATL 0x08
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#define GIUINTSTATH 0x0a
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#define GIUINTENL 0x0c
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#define GIUINTENH 0x0e
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#define GIUINTTYPL 0x10
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#define GIUINTTYPH 0x12
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#define GIUINTALSELL 0x14
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#define GIUINTALSELH 0x16
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#define GIUINTHTSELL 0x18
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#define GIUINTHTSELH 0x1a
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#define GIUPODATL 0x1c
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#define GIUPODATEN 0x1c
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#define GIUPODATH 0x1e
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#define PIOEN0 0x0100
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#define PIOEN1 0x0200
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#define GIUPODAT 0x1e
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#define GIUFEDGEINHL 0x20
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#define GIUFEDGEINHH 0x22
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#define GIUREDGEINHL 0x24
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#define GIUREDGEINHH 0x26
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#define GIUUSEUPDN 0x1e0
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#define GIUTERMUPDN 0x1e2
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#define GPIO_HAS_PULLUPDOWN_IO 0x0001
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#define GPIO_HAS_OUTPUT_ENABLE 0x0002
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#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
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static spinlock_t giu_lock;
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static unsigned long giu_flags;
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static unsigned int giu_nr_pins;
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static void __iomem *giu_base;
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#define giu_read(offset) readw(giu_base + (offset))
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#define giu_write(offset, value) writew((value), giu_base + (offset))
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#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
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#define GIUINT_HIGH_OFFSET 16
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#define GIUINT_HIGH_MAX 32
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static inline uint16_t giu_set(uint16_t offset, uint16_t set)
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{
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uint16_t data;
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data = giu_read(offset);
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data |= set;
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giu_write(offset, data);
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return data;
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}
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static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
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{
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uint16_t data;
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data = giu_read(offset);
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data &= ~clear;
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giu_write(offset, data);
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return data;
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}
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static void ack_giuint_low(unsigned int irq)
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{
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giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static void mask_giuint_low(unsigned int irq)
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{
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giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static void mask_ack_giuint_low(unsigned int irq)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(irq);
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giu_clear(GIUINTENL, 1 << pin);
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giu_write(GIUINTSTATL, 1 << pin);
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}
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static void unmask_giuint_low(unsigned int irq)
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{
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giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
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}
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static struct irq_chip giuint_low_irq_chip = {
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.name = "GIUINTL",
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.ack = ack_giuint_low,
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.mask = mask_giuint_low,
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.mask_ack = mask_ack_giuint_low,
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.unmask = unmask_giuint_low,
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};
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static void ack_giuint_high(unsigned int irq)
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{
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giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static void mask_giuint_high(unsigned int irq)
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{
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giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static void mask_ack_giuint_high(unsigned int irq)
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{
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unsigned int pin;
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pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
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giu_clear(GIUINTENH, 1 << pin);
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giu_write(GIUINTSTATH, 1 << pin);
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}
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static void unmask_giuint_high(unsigned int irq)
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{
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giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
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}
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static struct irq_chip giuint_high_irq_chip = {
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.name = "GIUINTH",
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.ack = ack_giuint_high,
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.mask = mask_giuint_high,
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.mask_ack = mask_ack_giuint_high,
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.unmask = unmask_giuint_high,
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};
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static int giu_get_irq(unsigned int irq)
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{
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uint16_t pendl, pendh, maskl, maskh;
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int i;
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pendl = giu_read(GIUINTSTATL);
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pendh = giu_read(GIUINTSTATH);
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maskl = giu_read(GIUINTENL);
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maskh = giu_read(GIUINTENH);
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maskl &= pendl;
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maskh &= pendh;
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if (maskl) {
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for (i = 0; i < 16; i++) {
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if (maskl & (1 << i))
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return GIU_IRQ(i);
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}
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} else if (maskh) {
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for (i = 0; i < 16; i++) {
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if (maskh & (1 << i))
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return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
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}
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}
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printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
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maskl, pendl, maskh, pendh);
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atomic_inc(&irq_err_count);
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return -EINVAL;
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}
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void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal)
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{
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uint16_t mask;
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if (pin < GIUINT_HIGH_OFFSET) {
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mask = 1 << pin;
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if (trigger != IRQ_TRIGGER_LEVEL) {
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giu_set(GIUINTTYPL, mask);
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if (signal == IRQ_SIGNAL_HOLD)
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giu_set(GIUINTHTSELL, mask);
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else
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giu_clear(GIUINTHTSELL, mask);
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if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
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switch (trigger) {
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case IRQ_TRIGGER_EDGE_FALLING:
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giu_set(GIUFEDGEINHL, mask);
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giu_clear(GIUREDGEINHL, mask);
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break;
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case IRQ_TRIGGER_EDGE_RISING:
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giu_clear(GIUFEDGEINHL, mask);
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giu_set(GIUREDGEINHL, mask);
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break;
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default:
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giu_set(GIUFEDGEINHL, mask);
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giu_set(GIUREDGEINHL, mask);
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break;
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}
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}
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPL, mask);
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giu_clear(GIUINTHTSELL, mask);
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_low_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATL, mask);
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} else if (pin < GIUINT_HIGH_MAX) {
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mask = 1 << (pin - GIUINT_HIGH_OFFSET);
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if (trigger != IRQ_TRIGGER_LEVEL) {
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giu_set(GIUINTTYPH, mask);
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if (signal == IRQ_SIGNAL_HOLD)
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giu_set(GIUINTHTSELH, mask);
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else
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giu_clear(GIUINTHTSELH, mask);
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if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
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switch (trigger) {
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case IRQ_TRIGGER_EDGE_FALLING:
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giu_set(GIUFEDGEINHH, mask);
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giu_clear(GIUREDGEINHH, mask);
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break;
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case IRQ_TRIGGER_EDGE_RISING:
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giu_clear(GIUFEDGEINHH, mask);
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giu_set(GIUREDGEINHH, mask);
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break;
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default:
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giu_set(GIUFEDGEINHH, mask);
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giu_set(GIUREDGEINHH, mask);
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break;
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}
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}
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_edge_irq);
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} else {
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giu_clear(GIUINTTYPH, mask);
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giu_clear(GIUINTHTSELH, mask);
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set_irq_chip_and_handler(GIU_IRQ(pin),
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&giuint_high_irq_chip,
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handle_level_irq);
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}
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giu_write(GIUINTSTATH, mask);
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}
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}
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EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
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void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
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{
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uint16_t mask;
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if (pin < GIUINT_HIGH_OFFSET) {
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mask = 1 << pin;
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if (level == IRQ_LEVEL_HIGH)
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giu_set(GIUINTALSELL, mask);
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else
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giu_clear(GIUINTALSELL, mask);
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giu_write(GIUINTSTATL, mask);
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} else if (pin < GIUINT_HIGH_MAX) {
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mask = 1 << (pin - GIUINT_HIGH_OFFSET);
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if (level == IRQ_LEVEL_HIGH)
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giu_set(GIUINTALSELH, mask);
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else
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giu_clear(GIUINTALSELH, mask);
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giu_write(GIUINTSTATH, mask);
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}
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}
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EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
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gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
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{
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uint16_t reg, mask;
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if (pin >= giu_nr_pins)
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return GPIO_DATA_INVAL;
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if (pin < 16) {
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reg = giu_read(GIUPIODL);
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mask = (uint16_t)1 << pin;
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} else if (pin < 32) {
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reg = giu_read(GIUPIODH);
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mask = (uint16_t)1 << (pin - 16);
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} else if (pin < 48) {
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reg = giu_read(GIUPODATL);
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mask = (uint16_t)1 << (pin - 32);
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} else {
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reg = giu_read(GIUPODATH);
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mask = (uint16_t)1 << (pin - 48);
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}
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if (reg & mask)
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return GPIO_DATA_HIGH;
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return GPIO_DATA_LOW;
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}
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EXPORT_SYMBOL_GPL(vr41xx_gpio_get_pin);
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int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
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{
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uint16_t offset, mask, reg;
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unsigned long flags;
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if (pin >= giu_nr_pins)
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return -EINVAL;
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if (pin < 16) {
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offset = GIUPIODL;
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mask = (uint16_t)1 << pin;
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} else if (pin < 32) {
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offset = GIUPIODH;
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mask = (uint16_t)1 << (pin - 16);
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} else if (pin < 48) {
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offset = GIUPODATL;
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mask = (uint16_t)1 << (pin - 32);
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} else {
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offset = GIUPODATH;
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mask = (uint16_t)1 << (pin - 48);
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}
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spin_lock_irqsave(&giu_lock, flags);
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reg = giu_read(offset);
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if (data == GPIO_DATA_HIGH)
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reg |= mask;
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else
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reg &= ~mask;
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giu_write(offset, reg);
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spin_unlock_irqrestore(&giu_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(vr41xx_gpio_set_pin);
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int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
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{
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uint16_t offset, mask, reg;
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unsigned long flags;
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if (pin >= giu_nr_pins)
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return -EINVAL;
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if (pin < 16) {
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offset = GIUIOSELL;
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mask = (uint16_t)1 << pin;
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} else if (pin < 32) {
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offset = GIUIOSELH;
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mask = (uint16_t)1 << (pin - 16);
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} else {
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if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
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offset = GIUPODATEN;
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mask = (uint16_t)1 << (pin - 32);
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} else {
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switch (pin) {
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case 48:
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offset = GIUPODATH;
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mask = PIOEN0;
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break;
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case 49:
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offset = GIUPODATH;
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mask = PIOEN1;
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break;
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default:
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return -EINVAL;
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}
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}
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}
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spin_lock_irqsave(&giu_lock, flags);
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reg = giu_read(offset);
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if (dir == GPIO_OUTPUT)
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reg |= mask;
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else
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reg &= ~mask;
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giu_write(offset, reg);
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spin_unlock_irqrestore(&giu_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(vr41xx_gpio_set_direction);
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int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
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{
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uint16_t reg, mask;
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unsigned long flags;
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if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
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return -EPERM;
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if (pin >= 15)
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return -EINVAL;
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mask = (uint16_t)1 << pin;
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spin_lock_irqsave(&giu_lock, flags);
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if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
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reg = giu_read(GIUTERMUPDN);
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if (pull == GPIO_PULL_UP)
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reg |= mask;
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else
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reg &= ~mask;
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giu_write(GIUTERMUPDN, reg);
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reg = giu_read(GIUUSEUPDN);
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reg |= mask;
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giu_write(GIUUSEUPDN, reg);
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} else {
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reg = giu_read(GIUUSEUPDN);
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reg &= ~mask;
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giu_write(GIUUSEUPDN, reg);
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}
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spin_unlock_irqrestore(&giu_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
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static ssize_t gpio_read(struct file *file, char __user *buf, size_t len,
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loff_t *ppos)
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{
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unsigned int pin;
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char value = '0';
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pin = iminor(file->f_path.dentry->d_inode);
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if (pin >= giu_nr_pins)
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return -EBADF;
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if (vr41xx_gpio_get_pin(pin) == GPIO_DATA_HIGH)
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value = '1';
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if (len <= 0)
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return -EFAULT;
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if (put_user(value, buf))
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return -EFAULT;
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return 1;
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}
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static ssize_t gpio_write(struct file *file, const char __user *data,
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size_t len, loff_t *ppos)
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{
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unsigned int pin;
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size_t i;
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char c;
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int retval = 0;
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pin = iminor(file->f_path.dentry->d_inode);
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if (pin >= giu_nr_pins)
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return -EBADF;
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for (i = 0; i < len; i++) {
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if (get_user(c, data + i))
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return -EFAULT;
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switch (c) {
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case '0':
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retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_LOW);
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break;
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case '1':
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retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_HIGH);
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break;
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case 'D':
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printk(KERN_INFO "GPIO%d: pull down\n", pin);
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retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DOWN);
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break;
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case 'd':
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printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
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retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
|
|
break;
|
|
case 'I':
|
|
printk(KERN_INFO "GPIO%d: input\n", pin);
|
|
retval = vr41xx_gpio_set_direction(pin, GPIO_INPUT);
|
|
break;
|
|
case 'O':
|
|
printk(KERN_INFO "GPIO%d: output\n", pin);
|
|
retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT);
|
|
break;
|
|
case 'o':
|
|
printk(KERN_INFO "GPIO%d: output disable\n", pin);
|
|
retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT_DISABLE);
|
|
break;
|
|
case 'P':
|
|
printk(KERN_INFO "GPIO%d: pull up\n", pin);
|
|
retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_UP);
|
|
break;
|
|
case 'p':
|
|
printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
|
|
retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (retval < 0)
|
|
break;
|
|
}
|
|
|
|
return i;
|
|
}
|
|
|
|
static int gpio_open(struct inode *inode, struct file *file)
|
|
{
|
|
unsigned int pin;
|
|
|
|
pin = iminor(inode);
|
|
if (pin >= giu_nr_pins)
|
|
return -EBADF;
|
|
|
|
return nonseekable_open(inode, file);
|
|
}
|
|
|
|
static int gpio_release(struct inode *inode, struct file *file)
|
|
{
|
|
unsigned int pin;
|
|
|
|
pin = iminor(inode);
|
|
if (pin >= giu_nr_pins)
|
|
return -EBADF;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations gpio_fops = {
|
|
.owner = THIS_MODULE,
|
|
.read = gpio_read,
|
|
.write = gpio_write,
|
|
.open = gpio_open,
|
|
.release = gpio_release,
|
|
};
|
|
|
|
static int __devinit giu_probe(struct platform_device *dev)
|
|
{
|
|
struct resource *res;
|
|
unsigned int trigger, i, pin;
|
|
struct irq_chip *chip;
|
|
int irq, retval;
|
|
|
|
switch (dev->id) {
|
|
case GPIO_50PINS_PULLUPDOWN:
|
|
giu_flags = GPIO_HAS_PULLUPDOWN_IO;
|
|
giu_nr_pins = 50;
|
|
break;
|
|
case GPIO_36PINS:
|
|
giu_nr_pins = 36;
|
|
break;
|
|
case GPIO_48PINS_EDGE_SELECT:
|
|
giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
|
|
giu_nr_pins = 48;
|
|
break;
|
|
default:
|
|
printk(KERN_ERR "GIU: unknown ID %d\n", dev->id);
|
|
return -ENODEV;
|
|
}
|
|
|
|
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -EBUSY;
|
|
|
|
giu_base = ioremap(res->start, res->end - res->start + 1);
|
|
if (!giu_base)
|
|
return -ENOMEM;
|
|
|
|
retval = register_chrdev(major, "GIU", &gpio_fops);
|
|
if (retval < 0) {
|
|
iounmap(giu_base);
|
|
giu_base = NULL;
|
|
return retval;
|
|
}
|
|
|
|
if (major == 0) {
|
|
major = retval;
|
|
printk(KERN_INFO "GIU: major number %d\n", major);
|
|
}
|
|
|
|
spin_lock_init(&giu_lock);
|
|
|
|
giu_write(GIUINTENL, 0);
|
|
giu_write(GIUINTENH, 0);
|
|
|
|
trigger = giu_read(GIUINTTYPH) << 16;
|
|
trigger |= giu_read(GIUINTTYPL);
|
|
for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
|
|
pin = GPIO_PIN_OF_IRQ(i);
|
|
if (pin < GIUINT_HIGH_OFFSET)
|
|
chip = &giuint_low_irq_chip;
|
|
else
|
|
chip = &giuint_high_irq_chip;
|
|
|
|
if (trigger & (1 << pin))
|
|
set_irq_chip_and_handler(i, chip, handle_edge_irq);
|
|
else
|
|
set_irq_chip_and_handler(i, chip, handle_level_irq);
|
|
|
|
}
|
|
|
|
irq = platform_get_irq(dev, 0);
|
|
if (irq < 0 || irq >= NR_IRQS)
|
|
return -EBUSY;
|
|
|
|
return cascade_irq(irq, giu_get_irq);
|
|
}
|
|
|
|
static int __devexit giu_remove(struct platform_device *dev)
|
|
{
|
|
if (giu_base) {
|
|
iounmap(giu_base);
|
|
giu_base = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver giu_device_driver = {
|
|
.probe = giu_probe,
|
|
.remove = __devexit_p(giu_remove),
|
|
.driver = {
|
|
.name = "GIU",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init vr41xx_giu_init(void)
|
|
{
|
|
return platform_driver_register(&giu_device_driver);
|
|
}
|
|
|
|
static void __exit vr41xx_giu_exit(void)
|
|
{
|
|
platform_driver_unregister(&giu_device_driver);
|
|
}
|
|
|
|
module_init(vr41xx_giu_init);
|
|
module_exit(vr41xx_giu_exit);
|