374 lines
10 KiB
C
374 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Watchdog driver for Marvell Armada 37xx SoCs
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*
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* Author: Marek Behun <marek.behun@nic.cz>
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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/*
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* There are four counters that can be used for watchdog on Armada 37xx.
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* The addresses for counter control registers are register base plus ID*0x10,
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* where ID is 0, 1, 2 or 3.
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*
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* In this driver we use IDs 0 and 1. Counter ID 1 is used as watchdog counter,
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* while counter ID 0 is used to implement pinging the watchdog: counter ID 1 is
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* set to restart counting from initial value on counter ID 0 end count event.
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* Pinging is done by forcing immediate end count event on counter ID 0.
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* If only one counter was used, pinging would have to be implemented by
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* disabling and enabling the counter, leaving the system in a vulnerable state
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* for a (really) short period of time.
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*
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* Counters ID 2 and 3 are enabled by default even before U-Boot loads,
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* therefore this driver does not provide a way to use them, eg. by setting a
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* property in device tree.
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*/
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#define CNTR_ID_RETRIGGER 0
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#define CNTR_ID_WDOG 1
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/* relative to cpu_misc */
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#define WDT_TIMER_SELECT 0x64
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#define WDT_TIMER_SELECT_MASK 0xf
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#define WDT_TIMER_SELECT_VAL BIT(CNTR_ID_WDOG)
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/* relative to reg */
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#define CNTR_CTRL(id) ((id) * 0x10)
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#define CNTR_CTRL_ENABLE 0x0001
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#define CNTR_CTRL_ACTIVE 0x0002
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#define CNTR_CTRL_MODE_MASK 0x000c
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#define CNTR_CTRL_MODE_ONESHOT 0x0000
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#define CNTR_CTRL_MODE_HWSIG 0x000c
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#define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
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#define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
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#define CNTR_CTRL_PRESCALE_MASK 0xff00
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#define CNTR_CTRL_PRESCALE_MIN 2
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#define CNTR_CTRL_PRESCALE_SHIFT 8
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#define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
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#define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
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#define WATCHDOG_TIMEOUT 120
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static unsigned int timeout;
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module_param(timeout, int, 0);
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MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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struct armada_37xx_watchdog {
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struct watchdog_device wdt;
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struct regmap *cpu_misc;
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void __iomem *reg;
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u64 timeout; /* in clock ticks */
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unsigned long clk_rate;
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struct clk *clk;
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};
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static u64 get_counter_value(struct armada_37xx_watchdog *dev, int id)
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{
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u64 val;
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/*
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* when low is read, high is latched into flip-flops so that it can be
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* read consistently without using software debouncing
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*/
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val = readl(dev->reg + CNTR_COUNT_LOW(id));
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val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32;
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return val;
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}
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static void set_counter_value(struct armada_37xx_watchdog *dev, int id, u64 val)
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{
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writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id));
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writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id));
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}
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static void counter_enable(struct armada_37xx_watchdog *dev, int id)
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{
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u32 reg;
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reg = readl(dev->reg + CNTR_CTRL(id));
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reg |= CNTR_CTRL_ENABLE;
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writel(reg, dev->reg + CNTR_CTRL(id));
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}
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static void counter_disable(struct armada_37xx_watchdog *dev, int id)
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{
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u32 reg;
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reg = readl(dev->reg + CNTR_CTRL(id));
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reg &= ~CNTR_CTRL_ENABLE;
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writel(reg, dev->reg + CNTR_CTRL(id));
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}
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static void init_counter(struct armada_37xx_watchdog *dev, int id, u32 mode,
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u32 trig_src)
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{
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u32 reg;
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reg = readl(dev->reg + CNTR_CTRL(id));
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reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
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CNTR_CTRL_TRIG_SRC_MASK);
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/* set mode */
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reg |= mode & CNTR_CTRL_MODE_MASK;
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/* set prescaler to the min value */
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reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
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/* set trigger source */
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reg |= trig_src & CNTR_CTRL_TRIG_SRC_MASK;
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writel(reg, dev->reg + CNTR_CTRL(id));
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}
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static int armada_37xx_wdt_ping(struct watchdog_device *wdt)
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{
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struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
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/* counter 1 is retriggered by forcing end count on counter 0 */
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counter_disable(dev, CNTR_ID_RETRIGGER);
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counter_enable(dev, CNTR_ID_RETRIGGER);
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return 0;
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}
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static unsigned int armada_37xx_wdt_get_timeleft(struct watchdog_device *wdt)
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{
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struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
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u64 res;
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res = get_counter_value(dev, CNTR_ID_WDOG) * CNTR_CTRL_PRESCALE_MIN;
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do_div(res, dev->clk_rate);
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return res;
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}
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static int armada_37xx_wdt_set_timeout(struct watchdog_device *wdt,
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unsigned int timeout)
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{
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struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
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wdt->timeout = timeout;
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/*
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* Compute the timeout in clock rate. We use smallest possible
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* prescaler, which divides the clock rate by 2
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* (CNTR_CTRL_PRESCALE_MIN).
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*/
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dev->timeout = (u64)dev->clk_rate * timeout;
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do_div(dev->timeout, CNTR_CTRL_PRESCALE_MIN);
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return 0;
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}
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static bool armada_37xx_wdt_is_running(struct armada_37xx_watchdog *dev)
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{
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u32 reg;
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regmap_read(dev->cpu_misc, WDT_TIMER_SELECT, ®);
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if ((reg & WDT_TIMER_SELECT_MASK) != WDT_TIMER_SELECT_VAL)
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return false;
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reg = readl(dev->reg + CNTR_CTRL(CNTR_ID_WDOG));
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return !!(reg & CNTR_CTRL_ACTIVE);
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}
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static int armada_37xx_wdt_start(struct watchdog_device *wdt)
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{
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struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
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/* select counter 1 as watchdog counter */
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regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, WDT_TIMER_SELECT_VAL);
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/* init counter 0 as retrigger counter for counter 1 */
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init_counter(dev, CNTR_ID_RETRIGGER, CNTR_CTRL_MODE_ONESHOT, 0);
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set_counter_value(dev, CNTR_ID_RETRIGGER, 0);
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/* init counter 1 to be retriggerable by counter 0 end count */
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init_counter(dev, CNTR_ID_WDOG, CNTR_CTRL_MODE_HWSIG,
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CNTR_CTRL_TRIG_SRC_PREV_CNTR);
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set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
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/* enable counter 1 */
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counter_enable(dev, CNTR_ID_WDOG);
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/* start counter 1 by forcing immediate end count on counter 0 */
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counter_enable(dev, CNTR_ID_RETRIGGER);
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return 0;
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}
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static int armada_37xx_wdt_stop(struct watchdog_device *wdt)
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{
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struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
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counter_disable(dev, CNTR_ID_WDOG);
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counter_disable(dev, CNTR_ID_RETRIGGER);
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regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, 0);
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return 0;
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}
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static const struct watchdog_info armada_37xx_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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.identity = "Armada 37xx Watchdog",
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};
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static const struct watchdog_ops armada_37xx_wdt_ops = {
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.owner = THIS_MODULE,
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.start = armada_37xx_wdt_start,
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.stop = armada_37xx_wdt_stop,
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.ping = armada_37xx_wdt_ping,
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.set_timeout = armada_37xx_wdt_set_timeout,
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.get_timeleft = armada_37xx_wdt_get_timeleft,
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};
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static void armada_clk_disable_unprepare(void *data)
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{
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clk_disable_unprepare(data);
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}
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static int armada_37xx_wdt_probe(struct platform_device *pdev)
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{
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struct armada_37xx_watchdog *dev;
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struct resource *res;
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struct regmap *regmap;
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int ret;
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dev = devm_kzalloc(&pdev->dev, sizeof(struct armada_37xx_watchdog),
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GFP_KERNEL);
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if (!dev)
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return -ENOMEM;
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dev->wdt.info = &armada_37xx_wdt_info;
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dev->wdt.ops = &armada_37xx_wdt_ops;
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regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"marvell,system-controller");
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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dev->cpu_misc = regmap;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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dev->reg = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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/* init clock */
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dev->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dev->clk))
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return PTR_ERR(dev->clk);
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ret = clk_prepare_enable(dev->clk);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(&pdev->dev,
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armada_clk_disable_unprepare, dev->clk);
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if (ret)
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return ret;
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dev->clk_rate = clk_get_rate(dev->clk);
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if (!dev->clk_rate)
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return -EINVAL;
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/*
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* Since the timeout in seconds is given as 32 bit unsigned int, and
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* the counters hold 64 bit values, even after multiplication by clock
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* rate the counter can hold timeout of UINT_MAX seconds.
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*/
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dev->wdt.min_timeout = 1;
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dev->wdt.max_timeout = UINT_MAX;
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dev->wdt.parent = &pdev->dev;
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/* default value, possibly override by module parameter or dtb */
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dev->wdt.timeout = WATCHDOG_TIMEOUT;
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watchdog_init_timeout(&dev->wdt, timeout, &pdev->dev);
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platform_set_drvdata(pdev, &dev->wdt);
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watchdog_set_drvdata(&dev->wdt, dev);
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armada_37xx_wdt_set_timeout(&dev->wdt, dev->wdt.timeout);
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if (armada_37xx_wdt_is_running(dev))
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set_bit(WDOG_HW_RUNNING, &dev->wdt.status);
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watchdog_set_nowayout(&dev->wdt, nowayout);
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watchdog_stop_on_reboot(&dev->wdt);
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ret = devm_watchdog_register_device(&pdev->dev, &dev->wdt);
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if (ret)
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return ret;
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dev_info(&pdev->dev, "Initial timeout %d sec%s\n",
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dev->wdt.timeout, nowayout ? ", nowayout" : "");
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return 0;
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}
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static int __maybe_unused armada_37xx_wdt_suspend(struct device *dev)
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{
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struct watchdog_device *wdt = dev_get_drvdata(dev);
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return armada_37xx_wdt_stop(wdt);
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}
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static int __maybe_unused armada_37xx_wdt_resume(struct device *dev)
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{
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struct watchdog_device *wdt = dev_get_drvdata(dev);
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if (watchdog_active(wdt))
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return armada_37xx_wdt_start(wdt);
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return 0;
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}
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static const struct dev_pm_ops armada_37xx_wdt_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(armada_37xx_wdt_suspend,
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armada_37xx_wdt_resume)
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};
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#ifdef CONFIG_OF
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static const struct of_device_id armada_37xx_wdt_match[] = {
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{ .compatible = "marvell,armada-3700-wdt", },
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{},
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};
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MODULE_DEVICE_TABLE(of, armada_37xx_wdt_match);
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#endif
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static struct platform_driver armada_37xx_wdt_driver = {
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.probe = armada_37xx_wdt_probe,
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.driver = {
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.name = "armada_37xx_wdt",
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.of_match_table = of_match_ptr(armada_37xx_wdt_match),
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.pm = &armada_37xx_wdt_dev_pm_ops,
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},
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};
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module_platform_driver(armada_37xx_wdt_driver);
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MODULE_AUTHOR("Marek Behun <marek.behun@nic.cz>");
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MODULE_DESCRIPTION("Armada 37xx CPU Watchdog");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:armada_37xx_wdt");
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