611 lines
19 KiB
C
611 lines
19 KiB
C
/*
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*
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* Copyright 2008 (c) Intel Corporation
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* Jesse Barnes <jbarnes@virtuousgeek.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (pipe == PIPE_A)
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return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
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else
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return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
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}
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static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
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u32 *array;
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int i;
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if (!i915_pipe_enabled(dev, pipe))
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return;
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if (pipe == PIPE_A)
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array = dev_priv->save_palette_a;
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else
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array = dev_priv->save_palette_b;
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for(i = 0; i < 256; i++)
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array[i] = I915_READ(reg + (i << 2));
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}
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static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
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u32 *array;
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int i;
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if (!i915_pipe_enabled(dev, pipe))
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return;
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if (pipe == PIPE_A)
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array = dev_priv->save_palette_a;
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else
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array = dev_priv->save_palette_b;
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for(i = 0; i < 256; i++)
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I915_WRITE(reg + (i << 2), array[i]);
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}
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static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE8(index_port, reg);
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return I915_READ8(data_port);
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}
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static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
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return I915_READ8(VGA_AR_DATA_READ);
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}
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static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
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I915_WRITE8(VGA_AR_DATA_WRITE, val);
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}
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static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE8(index_port, reg);
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I915_WRITE8(data_port, val);
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}
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static void i915_save_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* VGA color palette registers */
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dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
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/* MSR bits */
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dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
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if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* CRT controller regs */
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i915_write_indexed(dev, cr_index, cr_data, 0x11,
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i915_read_indexed(dev, cr_index, cr_data, 0x11) &
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(~0x80));
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for (i = 0; i <= 0x24; i++)
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dev_priv->saveCR[i] =
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i915_read_indexed(dev, cr_index, cr_data, i);
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/* Make sure we don't turn off CR group 0 writes */
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dev_priv->saveCR[0x11] &= ~0x80;
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/* Attribute controller registers */
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I915_READ8(st01);
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dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
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for (i = 0; i <= 0x14; i++)
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dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
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I915_READ8(st01);
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/* Graphics controller registers */
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for (i = 0; i < 9; i++)
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dev_priv->saveGR[i] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
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dev_priv->saveGR[0x10] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
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dev_priv->saveGR[0x11] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
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dev_priv->saveGR[0x18] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
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/* Sequencer registers */
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for (i = 0; i < 8; i++)
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dev_priv->saveSR[i] =
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i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
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}
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static void i915_restore_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* MSR bits */
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I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
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if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* Sequencer registers, don't write SR07 */
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for (i = 0; i < 7; i++)
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i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
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dev_priv->saveSR[i]);
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/* CRT controller regs */
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/* Enable CR group 0 writes */
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i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
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for (i = 0; i <= 0x24; i++)
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i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
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/* Graphics controller regs */
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for (i = 0; i < 9; i++)
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
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dev_priv->saveGR[i]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
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dev_priv->saveGR[0x10]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
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dev_priv->saveGR[0x11]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
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dev_priv->saveGR[0x18]);
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/* Attribute controller registers */
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I915_READ8(st01); /* switch back to index mode */
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for (i = 0; i <= 0x14; i++)
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i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
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I915_READ8(st01); /* switch back to index mode */
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I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
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I915_READ8(st01);
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/* VGA color palette registers */
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I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
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}
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static void i915_save_modeset_reg(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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/* Pipe & plane A info */
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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dev_priv->saveFPA0 = I915_READ(FPA0);
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dev_priv->saveFPA1 = I915_READ(FPA1);
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dev_priv->saveDPLL_A = I915_READ(DPLL_A);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
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dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
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dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
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dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
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dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
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dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
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dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
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dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
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dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
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dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
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dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
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dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
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dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
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if (IS_I965G(dev)) {
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dev_priv->saveDSPASURF = I915_READ(DSPASURF);
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dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
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}
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i915_save_palette(dev, PIPE_A);
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dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
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/* Pipe & plane B info */
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dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
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dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
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dev_priv->saveFPB0 = I915_READ(FPB0);
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dev_priv->saveFPB1 = I915_READ(FPB1);
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dev_priv->saveDPLL_B = I915_READ(DPLL_B);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
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dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
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dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
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dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
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dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
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dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
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dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
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dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
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dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
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dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
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dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
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dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
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dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
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if (IS_I965GM(dev) || IS_GM45(dev)) {
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dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
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dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
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}
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i915_save_palette(dev, PIPE_B);
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dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
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return;
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}
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static void i915_restore_modeset_reg(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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/* Pipe & plane A info */
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/* Prime the clock */
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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}
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I915_WRITE(FPA0, dev_priv->saveFPA0);
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I915_WRITE(FPA1, dev_priv->saveFPA1);
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/* Actually enable it */
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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DRM_UDELAY(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
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DRM_UDELAY(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
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I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
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I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
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I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
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I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
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I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
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I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
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/* Restore plane info */
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I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
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I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
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I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
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I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
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I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
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if (IS_I965G(dev)) {
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I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
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I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
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}
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I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
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i915_restore_palette(dev, PIPE_A);
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/* Enable the plane */
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I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
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I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
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/* Pipe & plane B info */
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if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
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~DPLL_VCO_ENABLE);
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DRM_UDELAY(150);
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}
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I915_WRITE(FPB0, dev_priv->saveFPB0);
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I915_WRITE(FPB1, dev_priv->saveFPB1);
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/* Actually enable it */
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I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
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DRM_UDELAY(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
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DRM_UDELAY(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
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I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
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I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
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I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
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I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
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I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
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I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
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/* Restore plane info */
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I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
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I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
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I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
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I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
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I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
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if (IS_I965G(dev)) {
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I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
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I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
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}
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I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
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i915_restore_palette(dev, PIPE_B);
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/* Enable the plane */
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I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
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I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
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return;
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}
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int i915_save_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
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/* Hardware status page */
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dev_priv->saveHWS = I915_READ(HWS_PGA);
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/* Display arbitration control */
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dev_priv->saveDSPARB = I915_READ(DSPARB);
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/* This is only meaningful in non-KMS mode */
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/* Don't save them in KMS mode */
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i915_save_modeset_reg(dev);
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/* Cursor state */
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dev_priv->saveCURACNTR = I915_READ(CURACNTR);
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dev_priv->saveCURAPOS = I915_READ(CURAPOS);
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dev_priv->saveCURABASE = I915_READ(CURABASE);
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dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
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dev_priv->saveCURBPOS = I915_READ(CURBPOS);
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dev_priv->saveCURBBASE = I915_READ(CURBBASE);
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if (!IS_I9XX(dev))
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dev_priv->saveCURSIZE = I915_READ(CURSIZE);
|
|
|
|
/* CRT state */
|
|
dev_priv->saveADPA = I915_READ(ADPA);
|
|
|
|
/* LVDS state */
|
|
dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
|
|
dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
|
|
dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
|
|
if (IS_I965G(dev))
|
|
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
|
|
if (IS_MOBILE(dev) && !IS_I830(dev))
|
|
dev_priv->saveLVDS = I915_READ(LVDS);
|
|
if (!IS_I830(dev) && !IS_845G(dev))
|
|
dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
|
|
dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
|
|
dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
|
|
dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
|
|
|
|
/* Display Port state */
|
|
if (SUPPORTS_INTEGRATED_DP(dev)) {
|
|
dev_priv->saveDP_B = I915_READ(DP_B);
|
|
dev_priv->saveDP_C = I915_READ(DP_C);
|
|
dev_priv->saveDP_D = I915_READ(DP_D);
|
|
dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
|
|
dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
|
|
dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
|
|
dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
|
|
dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
|
|
dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
|
|
dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
|
|
dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
|
|
}
|
|
/* FIXME: save TV & SDVO state */
|
|
|
|
/* FBC state */
|
|
dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
|
|
dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
|
|
dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
|
|
dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
|
|
|
|
/* Interrupt state */
|
|
dev_priv->saveIIR = I915_READ(IIR);
|
|
dev_priv->saveIER = I915_READ(IER);
|
|
dev_priv->saveIMR = I915_READ(IMR);
|
|
|
|
/* VGA state */
|
|
dev_priv->saveVGA0 = I915_READ(VGA0);
|
|
dev_priv->saveVGA1 = I915_READ(VGA1);
|
|
dev_priv->saveVGA_PD = I915_READ(VGA_PD);
|
|
dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
|
|
|
|
/* Clock gating state */
|
|
dev_priv->saveD_STATE = I915_READ(D_STATE);
|
|
dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
|
|
|
|
/* Cache mode state */
|
|
dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
|
|
|
|
/* Memory Arbitration state */
|
|
dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
|
|
|
|
/* Scratch space */
|
|
for (i = 0; i < 16; i++) {
|
|
dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
|
|
dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
|
|
}
|
|
for (i = 0; i < 3; i++)
|
|
dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
|
|
|
|
/* Fences */
|
|
if (IS_I965G(dev)) {
|
|
for (i = 0; i < 16; i++)
|
|
dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
|
|
} else {
|
|
for (i = 0; i < 8; i++)
|
|
dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
|
|
|
|
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
|
for (i = 0; i < 8; i++)
|
|
dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
|
|
}
|
|
i915_save_vga(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_restore_state(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int i;
|
|
|
|
pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
|
|
|
|
/* Render Standby */
|
|
if (IS_I965G(dev) && IS_MOBILE(dev))
|
|
I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
|
|
|
|
/* Hardware status page */
|
|
I915_WRITE(HWS_PGA, dev_priv->saveHWS);
|
|
|
|
/* Display arbitration */
|
|
I915_WRITE(DSPARB, dev_priv->saveDSPARB);
|
|
|
|
/* Fences */
|
|
if (IS_I965G(dev)) {
|
|
for (i = 0; i < 16; i++)
|
|
I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
|
|
} else {
|
|
for (i = 0; i < 8; i++)
|
|
I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
|
|
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
|
for (i = 0; i < 8; i++)
|
|
I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
|
|
}
|
|
|
|
/* Display port ratios (must be done before clock is set) */
|
|
if (SUPPORTS_INTEGRATED_DP(dev)) {
|
|
I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
|
|
I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
|
|
I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
|
|
I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
|
|
I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
|
|
I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
|
|
I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
|
|
I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
|
|
}
|
|
/* This is only meaningful in non-KMS mode */
|
|
/* Don't restore them in KMS mode */
|
|
i915_restore_modeset_reg(dev);
|
|
/* Cursor state */
|
|
I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
|
|
I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
|
|
I915_WRITE(CURABASE, dev_priv->saveCURABASE);
|
|
I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
|
|
I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
|
|
I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
|
|
if (!IS_I9XX(dev))
|
|
I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
|
|
|
|
/* CRT state */
|
|
I915_WRITE(ADPA, dev_priv->saveADPA);
|
|
|
|
/* LVDS state */
|
|
if (IS_I965G(dev))
|
|
I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
|
|
if (IS_MOBILE(dev) && !IS_I830(dev))
|
|
I915_WRITE(LVDS, dev_priv->saveLVDS);
|
|
if (!IS_I830(dev) && !IS_845G(dev))
|
|
I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
|
|
|
|
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
|
|
I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
|
|
I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
|
|
I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
|
|
I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
|
|
I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
|
|
|
|
/* Display Port state */
|
|
if (SUPPORTS_INTEGRATED_DP(dev)) {
|
|
I915_WRITE(DP_B, dev_priv->saveDP_B);
|
|
I915_WRITE(DP_C, dev_priv->saveDP_C);
|
|
I915_WRITE(DP_D, dev_priv->saveDP_D);
|
|
}
|
|
/* FIXME: restore TV & SDVO state */
|
|
|
|
/* FBC info */
|
|
I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
|
|
I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
|
|
I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
|
|
I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
|
|
|
|
/* VGA state */
|
|
I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
|
|
I915_WRITE(VGA0, dev_priv->saveVGA0);
|
|
I915_WRITE(VGA1, dev_priv->saveVGA1);
|
|
I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
|
|
DRM_UDELAY(150);
|
|
|
|
/* Clock gating state */
|
|
I915_WRITE (D_STATE, dev_priv->saveD_STATE);
|
|
I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
|
|
|
|
/* Cache mode state */
|
|
I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
|
|
|
|
/* Memory arbitration state */
|
|
I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
|
|
I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
|
|
}
|
|
for (i = 0; i < 3; i++)
|
|
I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
|
|
|
|
i915_restore_vga(dev);
|
|
|
|
return 0;
|
|
}
|
|
|