391 lines
10 KiB
C
391 lines
10 KiB
C
/*
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* arch/arm/mach-at91/at91sam9260.c
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*
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* Copyright (C) 2006 SAN People
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <asm/proc-fns.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/cpu.h>
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#include <mach/at91_dbgu.h>
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#include <mach/at91sam9260.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_rstc.h>
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#include "soc.h"
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#include "generic.h"
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#include "clock.h"
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#include "sam9_smc.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udc_clk = {
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.name = "udc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi_clk = {
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.name = "twi_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TWI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc_clk = {
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.name = "ssc_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_SSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ohci_clk = {
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.name = "ohci_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk macb_clk = {
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.name = "pclk",
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.pmc_mask = 1 << AT91SAM9260_ID_EMAC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk isi_clk = {
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.name = "isi_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_ISI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart4_clk = {
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.name = "usart4_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart5_clk = {
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.name = "usart5_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_US5,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc3_clk = {
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.name = "tc3_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc4_clk = {
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.name = "tc4_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC4,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc5_clk = {
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.name = "tc5_clk",
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.pmc_mask = 1 << AT91SAM9260_ID_TC5,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&adc_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&mmc_clk,
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&udc_clk,
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&twi_clk,
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&spi0_clk,
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&spi1_clk,
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&ssc_clk,
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&ohci_clk,
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&macb_clk,
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&isi_clk,
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&usart3_clk,
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&usart4_clk,
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&usart5_clk,
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&tc3_clk,
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&tc4_clk,
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&tc5_clk,
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// irq0 .. irq2
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* One additional fake clock for macb_hclk */
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CLKDEV_CON_ID("hclk", &macb_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
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CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
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CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
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CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
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/* more usart lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
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CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
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CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
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CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
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/* fake hclk clock */
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CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
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CLKDEV_CON_ID("pioA", &pioA_clk),
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CLKDEV_CON_ID("pioB", &pioB_clk),
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CLKDEV_CON_ID("pioC", &pioC_clk),
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};
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static struct clk_lookup usart_clocks_lookups[] = {
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
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CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9260_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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clkdev_add_table(usart_clocks_lookups,
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ARRAY_SIZE(usart_clocks_lookups));
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clk_register(&pck0);
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clk_register(&pck1);
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}
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static struct clk_lookup console_clock_lookup;
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void __init at91sam9260_set_console_clock(int id)
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{
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if (id >= ARRAY_SIZE(usart_clocks_lookups))
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return;
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console_clock_lookup.con_id = "usart";
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console_clock_lookup.clk = usart_clocks_lookups[id].clk;
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clkdev_add(&console_clock_lookup);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
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{
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.id = AT91SAM9260_ID_PIOA,
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.regbase = AT91SAM9260_BASE_PIOA,
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}, {
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.id = AT91SAM9260_ID_PIOB,
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.regbase = AT91SAM9260_BASE_PIOB,
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}, {
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.id = AT91SAM9260_ID_PIOC,
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.regbase = AT91SAM9260_BASE_PIOC,
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}
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};
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/* --------------------------------------------------------------------
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* AT91SAM9260 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9xe_map_io(void)
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{
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unsigned long sram_size;
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switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
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case AT91_CIDR_SRAMSIZ_32K:
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sram_size = 2 * SZ_16K;
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break;
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case AT91_CIDR_SRAMSIZ_16K:
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default:
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sram_size = SZ_16K;
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}
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at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
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}
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static void __init at91sam9260_map_io(void)
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{
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if (cpu_is_at91sam9xe())
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at91sam9xe_map_io();
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else if (cpu_is_at91sam9g20())
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at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
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else
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at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
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}
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static void __init at91sam9260_ioremap_registers(void)
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{
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at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
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at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
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at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
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at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
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at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
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at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
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}
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static void __init at91sam9260_initialize(void)
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{
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arm_pm_idle = at91sam9_idle;
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arm_pm_restart = at91sam9_alt_restart;
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at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
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| (1 << AT91SAM9260_ID_IRQ2);
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9260_gpio, 3);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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0, /* Analog-to-Digital Converter */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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0, /* Multimedia Card Interface */
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2, /* USB Device Port */
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6, /* Two-Wire Interface */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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5, /* Serial Synchronous Controller */
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0,
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0,
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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2, /* USB Host port */
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3, /* Ethernet */
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0, /* Image Sensor Interface */
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5, /* USART 3 */
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5, /* USART 4 */
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5, /* USART 5 */
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0, /* Timer Counter 3 */
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0, /* Timer Counter 4 */
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0, /* Timer Counter 5 */
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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0, /* Advanced Interrupt Controller */
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};
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struct at91_init_soc __initdata at91sam9260_soc = {
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.map_io = at91sam9260_map_io,
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.default_irq_priority = at91sam9260_default_irq_priority,
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.ioremap_registers = at91sam9260_ioremap_registers,
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.register_clocks = at91sam9260_register_clocks,
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.init = at91sam9260_initialize,
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};
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