428 lines
12 KiB
C
428 lines
12 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author: Jani Nikula <jani.nikula@intel.com>
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*/
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#include <linux/export.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <video/mipi_display.h>
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include "intel_dsi.h"
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#include "intel_dsi_cmd.h"
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/*
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* XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
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* MIPI_COMMAND_ADDRESS registers.
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*
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* Apparently these registers provide a MIPI adapter level way to send (lots of)
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* commands and data to the receiver, without having to write the commands and
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* data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
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*
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* Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
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* MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
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* framebuffer in command mode displays) these are just an optimization that can
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* come later.
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*
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* For memory writes, these should probably be used for performance.
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*/
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static void print_stat(struct intel_dsi *intel_dsi)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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u32 val;
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val = I915_READ(MIPI_INTR_STAT(pipe));
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#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
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DRM_DEBUG_KMS("MIPI_INTR_STAT(%d) = %08x"
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"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
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"\n", pipe, val,
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STAT_BIT(val, TEARING_EFFECT),
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STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
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STAT_BIT(val, GEN_READ_DATA_AVAIL),
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STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
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STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
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STAT_BIT(val, RX_PROT_VIOLATION),
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STAT_BIT(val, RX_INVALID_TX_LENGTH),
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STAT_BIT(val, ACK_WITH_NO_ERROR),
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STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
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STAT_BIT(val, LP_RX_TIMEOUT),
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STAT_BIT(val, HS_TX_TIMEOUT),
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STAT_BIT(val, DPI_FIFO_UNDERRUN),
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STAT_BIT(val, LOW_CONTENTION),
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STAT_BIT(val, HIGH_CONTENTION),
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STAT_BIT(val, TXDSI_VC_ID_INVALID),
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STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
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STAT_BIT(val, TXCHECKSUM_ERROR),
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STAT_BIT(val, TXECC_MULTIBIT_ERROR),
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STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
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STAT_BIT(val, TXFALSE_CONTROL_ERROR),
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STAT_BIT(val, RXDSI_VC_ID_INVALID),
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STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
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STAT_BIT(val, RXCHECKSUM_ERROR),
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STAT_BIT(val, RXECC_MULTIBIT_ERROR),
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STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
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STAT_BIT(val, RXFALSE_CONTROL_ERROR),
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STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
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STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
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STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
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STAT_BIT(val, RXEOT_SYNC_ERROR),
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STAT_BIT(val, RXSOT_SYNC_ERROR),
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STAT_BIT(val, RXSOT_ERROR));
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#undef STAT_BIT
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}
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enum dsi_type {
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DSI_DCS,
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DSI_GENERIC,
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};
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/* enable or disable command mode hs transmissions */
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void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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u32 temp;
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u32 mask = DBI_FIFO_EMPTY;
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if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
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DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
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temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(pipe));
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temp &= DBI_HS_LP_MODE_MASK;
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I915_WRITE(MIPI_HS_LP_DBI_ENABLE(pipe), enable ? DBI_HS_MODE : DBI_LP_MODE);
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intel_dsi->hs = enable;
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}
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static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
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u8 data_type, u16 data)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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u32 ctrl_reg;
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u32 ctrl;
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u32 mask;
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DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
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channel, data_type, data);
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if (intel_dsi->hs) {
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ctrl_reg = MIPI_HS_GEN_CTRL(pipe);
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mask = HS_CTRL_FIFO_FULL;
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} else {
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ctrl_reg = MIPI_LP_GEN_CTRL(pipe);
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mask = LP_CTRL_FIFO_FULL;
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}
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if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50)) {
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DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
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print_stat(intel_dsi);
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}
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/*
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* Note: This function is also used for long packets, with length passed
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* as data, since SHORT_PACKET_PARAM_SHIFT ==
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* LONG_PACKET_WORD_COUNT_SHIFT.
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*/
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ctrl = data << SHORT_PACKET_PARAM_SHIFT |
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channel << VIRTUAL_CHANNEL_SHIFT |
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data_type << DATA_TYPE_SHIFT;
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I915_WRITE(ctrl_reg, ctrl);
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return 0;
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}
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static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
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u8 data_type, const u8 *data, int len)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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u32 data_reg;
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int i, j, n;
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u32 mask;
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DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
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channel, data_type, len);
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if (intel_dsi->hs) {
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data_reg = MIPI_HS_GEN_DATA(pipe);
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mask = HS_DATA_FIFO_FULL;
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} else {
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data_reg = MIPI_LP_GEN_DATA(pipe);
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mask = LP_DATA_FIFO_FULL;
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}
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if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == 0, 50))
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DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
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for (i = 0; i < len; i += n) {
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u32 val = 0;
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n = min_t(int, len - i, 4);
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for (j = 0; j < n; j++)
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val |= *data++ << 8 * j;
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I915_WRITE(data_reg, val);
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/* XXX: check for data fifo full, once that is set, write 4
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* dwords, then wait for not set, then continue. */
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}
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return dsi_vc_send_short(intel_dsi, channel, data_type, len);
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}
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static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
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int channel, const u8 *data, int len,
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enum dsi_type type)
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{
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int ret;
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if (len == 0) {
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BUG_ON(type == DSI_GENERIC);
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ret = dsi_vc_send_short(intel_dsi, channel,
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MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
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0);
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} else if (len == 1) {
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ret = dsi_vc_send_short(intel_dsi, channel,
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type == DSI_GENERIC ?
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MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
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MIPI_DSI_DCS_SHORT_WRITE, data[0]);
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} else if (len == 2) {
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ret = dsi_vc_send_short(intel_dsi, channel,
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type == DSI_GENERIC ?
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MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
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MIPI_DSI_DCS_SHORT_WRITE_PARAM,
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(data[1] << 8) | data[0]);
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} else {
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ret = dsi_vc_send_long(intel_dsi, channel,
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type == DSI_GENERIC ?
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MIPI_DSI_GENERIC_LONG_WRITE :
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MIPI_DSI_DCS_LONG_WRITE, data, len);
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}
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return ret;
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}
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int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
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const u8 *data, int len)
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{
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return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS);
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}
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int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
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const u8 *data, int len)
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{
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return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC);
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}
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static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
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int channel, u8 dcs_cmd)
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{
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return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
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dcs_cmd);
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}
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static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
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int channel, u8 *reqdata,
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int reqlen)
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{
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u16 data;
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u8 data_type;
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switch (reqlen) {
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case 0:
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data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
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data = 0;
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break;
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case 1:
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data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
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data = reqdata[0];
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break;
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case 2:
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data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
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data = (reqdata[1] << 8) | reqdata[0];
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break;
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default:
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BUG();
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}
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return dsi_vc_send_short(intel_dsi, channel, data_type, data);
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}
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static int dsi_read_data_return(struct intel_dsi *intel_dsi,
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u8 *buf, int buflen)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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int i, len = 0;
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u32 data_reg, val;
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if (intel_dsi->hs) {
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data_reg = MIPI_HS_GEN_DATA(pipe);
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} else {
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data_reg = MIPI_LP_GEN_DATA(pipe);
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}
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while (len < buflen) {
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val = I915_READ(data_reg);
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for (i = 0; i < 4 && len < buflen; i++, len++)
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buf[len] = val >> 8 * i;
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}
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return len;
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}
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int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
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u8 *buf, int buflen)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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u32 mask;
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int ret;
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/*
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* XXX: should issue multiple read requests and reads if request is
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* longer than MIPI_MAX_RETURN_PKT_SIZE
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*/
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I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
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ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd);
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if (ret)
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return ret;
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mask = GEN_READ_DATA_AVAIL;
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if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
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DRM_ERROR("Timeout waiting for read data.\n");
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ret = dsi_read_data_return(intel_dsi, buf, buflen);
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if (ret < 0)
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return ret;
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if (ret != buflen)
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return -EIO;
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return 0;
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}
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int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
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u8 *reqdata, int reqlen, u8 *buf, int buflen)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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u32 mask;
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int ret;
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/*
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* XXX: should issue multiple read requests and reads if request is
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* longer than MIPI_MAX_RETURN_PKT_SIZE
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*/
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I915_WRITE(MIPI_INTR_STAT(pipe), GEN_READ_DATA_AVAIL);
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ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
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reqlen);
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if (ret)
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return ret;
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mask = GEN_READ_DATA_AVAIL;
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if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 50))
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DRM_ERROR("Timeout waiting for read data.\n");
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ret = dsi_read_data_return(intel_dsi, buf, buflen);
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if (ret < 0)
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return ret;
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if (ret != buflen)
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return -EIO;
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return 0;
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}
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/*
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* send a video mode command
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*
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* XXX: commands with data in MIPI_DPI_DATA?
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*/
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int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd)
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{
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struct drm_encoder *encoder = &intel_dsi->base.base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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enum pipe pipe = intel_crtc->pipe;
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u32 mask;
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/* XXX: pipe, hs */
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if (intel_dsi->hs)
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cmd &= ~DPI_LP_MODE;
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else
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cmd |= DPI_LP_MODE;
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/* DPI virtual channel?! */
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mask = DPI_FIFO_EMPTY;
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if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
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DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
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/* clear bit */
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I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
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/* XXX: old code skips write if control unchanged */
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if (cmd == I915_READ(MIPI_DPI_CONTROL(pipe)))
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DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
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I915_WRITE(MIPI_DPI_CONTROL(pipe), cmd);
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mask = SPL_PKT_SENT_INTERRUPT;
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if (wait_for((I915_READ(MIPI_INTR_STAT(pipe)) & mask) == mask, 100))
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DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
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return 0;
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}
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