88 lines
3.0 KiB
C
88 lines
3.0 KiB
C
#ifndef _PPC_BOOT_DCR_H_
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#define _PPC_BOOT_DCR_H_
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#define mfdcr(rn) \
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({ \
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unsigned long rval; \
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asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
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rval; \
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})
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#define mtdcr(rn, val) \
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asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
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/* 440GP/440GX SDRAM controller DCRs */
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#define DCRN_SDRAM0_CFGADDR 0x010
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#define DCRN_SDRAM0_CFGDATA 0x011
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#define SDRAM0_B0CR 0x40
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#define SDRAM0_B1CR 0x44
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#define SDRAM0_B2CR 0x48
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#define SDRAM0_B3CR 0x4c
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static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
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#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
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#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
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#define SDRAM_CONFIG_BANK_SIZE(reg) \
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(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
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/* 440GP Clock, PM, chip control */
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#define DCRN_CPC0_SR 0x0b0
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#define DCRN_CPC0_ER 0x0b1
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#define DCRN_CPC0_FR 0x0b2
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#define DCRN_CPC0_SYS0 0x0e0
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#define CPC0_SYS0_TUNE 0xffc00000
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#define CPC0_SYS0_FBDV_MASK 0x003c0000
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#define CPC0_SYS0_FWDVA_MASK 0x00038000
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#define CPC0_SYS0_FWDVB_MASK 0x00007000
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#define CPC0_SYS0_OPDV_MASK 0x00000c00
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#define CPC0_SYS0_EPDV_MASK 0x00000300
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/* Helper macros to compute the actual clock divider values from the
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* encodings in the CPC0 register */
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#define CPC0_SYS0_FBDV(reg) \
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((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
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#define CPC0_SYS0_FWDVA(reg) \
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(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
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#define CPC0_SYS0_FWDVB(reg) \
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(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
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#define CPC0_SYS0_OPDV(reg) \
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((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
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#define CPC0_SYS0_EPDV(reg) \
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((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
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#define CPC0_SYS0_EXTSL 0x00000080
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#define CPC0_SYS0_RW_MASK 0x00000060
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#define CPC0_SYS0_RL 0x00000010
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#define CPC0_SYS0_ZMIISL_MASK 0x0000000c
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#define CPC0_SYS0_BYPASS 0x00000002
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#define CPC0_SYS0_NTO1 0x00000001
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#define DCRN_CPC0_SYS1 0x0e1
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#define DCRN_CPC0_CUST0 0x0e2
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#define DCRN_CPC0_CUST1 0x0e3
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#define DCRN_CPC0_STRP0 0x0e4
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#define DCRN_CPC0_STRP1 0x0e5
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#define DCRN_CPC0_STRP2 0x0e6
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#define DCRN_CPC0_STRP3 0x0e7
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#define DCRN_CPC0_GPIO 0x0e8
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#define DCRN_CPC0_PLB 0x0e9
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#define DCRN_CPC0_CR1 0x0ea
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#define DCRN_CPC0_CR0 0x0eb
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#define CPC0_CR0_SWE 0x80000000
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#define CPC0_CR0_CETE 0x40000000
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#define CPC0_CR0_U1FCS 0x20000000
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#define CPC0_CR0_U0DTE 0x10000000
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#define CPC0_CR0_U0DRE 0x08000000
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#define CPC0_CR0_U0DC 0x04000000
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#define CPC0_CR0_U1DTE 0x02000000
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#define CPC0_CR0_U1DRE 0x01000000
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#define CPC0_CR0_U1DC 0x00800000
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#define CPC0_CR0_U0EC 0x00400000
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#define CPC0_CR0_U1EC 0x00200000
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#define CPC0_CR0_UDIV_MASK 0x001f0000
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#define CPC0_CR0_UDIV(reg) \
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((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
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#define DCRN_CPC0_MIRQ0 0x0ec
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#define DCRN_CPC0_MIRQ1 0x0ed
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#define DCRN_CPC0_JTAGID 0x0ef
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#endif /* _PPC_BOOT_DCR_H_ */
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