174 lines
5.8 KiB
C
174 lines
5.8 KiB
C
/*
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* Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* Copyright 2009 Jonathan Corbet <corbet@lwn.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public
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* License as published by the Free Software Foundation;
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* either version 2, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
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* the implied warranty of MERCHANTABILITY or FITNESS FOR
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* A PARTICULAR PURPOSE.See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __VIA_CORE_H__
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#define __VIA_CORE_H__
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#include <linux/spinlock.h>
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#include <linux/pci.h>
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/*
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* A description of each known serial I2C/GPIO port.
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*/
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enum via_port_type {
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VIA_PORT_NONE = 0,
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VIA_PORT_I2C,
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VIA_PORT_GPIO,
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};
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enum via_port_mode {
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VIA_MODE_OFF = 0,
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VIA_MODE_I2C, /* Used as I2C port */
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VIA_MODE_GPIO, /* Two GPIO ports */
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};
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enum viafb_i2c_adap {
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VIA_PORT_26 = 0,
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VIA_PORT_31,
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VIA_PORT_25,
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VIA_PORT_2C,
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VIA_PORT_3D,
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};
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#define VIAFB_NUM_PORTS 5
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struct via_port_cfg {
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enum via_port_type type;
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enum via_port_mode mode;
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u16 io_port;
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u8 ioport_index;
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};
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/*
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* This is the global viafb "device" containing stuff needed by
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* all subdevs.
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*/
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struct viafb_dev {
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struct pci_dev *pdev;
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int chip_type;
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struct via_port_cfg *port_cfg;
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/*
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* Spinlock for access to device registers. Not yet
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* globally used.
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*/
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spinlock_t reg_lock;
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/*
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* The framebuffer MMIO region. Little, if anything, touches
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* this memory directly, and certainly nothing outside of the
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* framebuffer device itself. We *do* have to be able to allocate
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* chunks of this memory for other devices, though.
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*/
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unsigned long fbmem_start;
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long fbmem_len;
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void __iomem *fbmem;
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#if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE)
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long camera_fbmem_offset;
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long camera_fbmem_size;
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#endif
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/*
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* The MMIO region for device registers.
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*/
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unsigned long engine_start;
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unsigned long engine_len;
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void __iomem *engine_mmio;
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};
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/*
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* Interrupt management.
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*/
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void viafb_irq_enable(u32 mask);
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void viafb_irq_disable(u32 mask);
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/*
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* The global interrupt control register and its bits.
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*/
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#define VDE_INTERRUPT 0x200 /* Video interrupt flags/masks */
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#define VDE_I_DVISENSE 0x00000001 /* DVI sense int status */
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#define VDE_I_VBLANK 0x00000002 /* Vertical blank status */
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#define VDE_I_MCCFI 0x00000004 /* MCE compl. frame int status */
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#define VDE_I_VSYNC 0x00000008 /* VGA VSYNC int status */
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#define VDE_I_DMA0DDONE 0x00000010 /* DMA 0 descr done */
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#define VDE_I_DMA0TDONE 0x00000020 /* DMA 0 transfer done */
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#define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
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#define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
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#define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */
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#define VDE_I_HQV0 0x00000200 /* First HQV engine */
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#define VDE_I_HQV1 0x00000400 /* Second HQV engine */
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#define VDE_I_HQV1EN 0x00000800 /* Second HQV engine enable */
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#define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */
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#define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */
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#define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */
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#define VDE_I_VSYNC2 0x00008000 /* Sec. Disp. VSYNC */
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#define VDE_I_DVISNSEN 0x00010000 /* DVI sense enable */
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#define VDE_I_VSYNC2EN 0x00020000 /* Sec Disp VSYNC enable */
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#define VDE_I_MCCFIEN 0x00040000 /* MC comp frame int mask enable */
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#define VDE_I_VSYNCEN 0x00080000 /* VSYNC enable */
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#define VDE_I_DMA0DDEN 0x00100000 /* DMA 0 descr done enable */
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#define VDE_I_DMA0TDEN 0x00200000 /* DMA 0 trans done enable */
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#define VDE_I_DMA1DDEN 0x00400000 /* DMA 1 descr done enable */
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#define VDE_I_DMA1TDEN 0x00800000 /* DMA 1 trans done enable */
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#define VDE_I_C1AVEN 0x01000000 /* cap 1 act vid end enable */
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#define VDE_I_HQV0EN 0x02000000 /* First hqv engine enable */
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#define VDE_I_C1VBIEN 0x04000000 /* Cap 1 VBI end enable */
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#define VDE_I_LVDSSI 0x08000000 /* LVDS sense interrupt */
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#define VDE_I_C0AVEN 0x10000000 /* Cap 0 act vid end enable */
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#define VDE_I_C0VBIEN 0x20000000 /* Cap 0 VBI end enable */
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#define VDE_I_LVDSSIEN 0x40000000 /* LVDS Sense enable */
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#define VDE_I_ENABLE 0x80000000 /* Global interrupt enable */
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/*
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* DMA management.
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*/
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int viafb_request_dma(void);
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void viafb_release_dma(void);
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/* void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len); */
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int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg);
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/*
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* DMA Controller registers.
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*/
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#define VDMA_MR0 0xe00 /* Mod reg 0 */
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#define VDMA_MR_CHAIN 0x01 /* Chaining mode */
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#define VDMA_MR_TDIE 0x02 /* Transfer done int enable */
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#define VDMA_CSR0 0xe04 /* Control/status */
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#define VDMA_C_ENABLE 0x01 /* DMA Enable */
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#define VDMA_C_START 0x02 /* Start a transfer */
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#define VDMA_C_ABORT 0x04 /* Abort a transfer */
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#define VDMA_C_DONE 0x08 /* Transfer is done */
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#define VDMA_MARL0 0xe20 /* Mem addr low */
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#define VDMA_MARH0 0xe24 /* Mem addr high */
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#define VDMA_DAR0 0xe28 /* Device address */
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#define VDMA_DQWCR0 0xe2c /* Count (16-byte) */
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#define VDMA_TMR0 0xe30 /* Tile mode reg */
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#define VDMA_DPRL0 0xe34 /* Not sure */
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#define VDMA_DPR_IN 0x08 /* Inbound transfer to FB */
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#define VDMA_DPRH0 0xe38
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#define VDMA_PMR0 (0xe00 + 0x134) /* Pitch mode */
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/*
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* Useful stuff that probably belongs somewhere global.
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*/
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#define VGA_WIDTH 640
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#define VGA_HEIGHT 480
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#endif /* __VIA_CORE_H__ */
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