918 lines
26 KiB
C
918 lines
26 KiB
C
/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/usb.h>
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#include <linux/pci.h>
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#include <linux/dmapool.h>
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#include "xhci.h"
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/*
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* Allocates a generic ring segment from the ring pool, sets the dma address,
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* initializes the segment to zero, and sets the private next pointer to NULL.
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*
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* Section 4.11.1.1:
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* "All components of all Command and Transfer TRBs shall be initialized to '0'"
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*/
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static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
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{
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struct xhci_segment *seg;
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dma_addr_t dma;
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seg = kzalloc(sizeof *seg, flags);
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if (!seg)
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return 0;
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xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
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seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
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if (!seg->trbs) {
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kfree(seg);
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return 0;
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}
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xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
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seg->trbs, (unsigned long long)dma);
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memset(seg->trbs, 0, SEGMENT_SIZE);
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seg->dma = dma;
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seg->next = NULL;
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return seg;
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}
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static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
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{
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if (!seg)
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return;
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if (seg->trbs) {
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xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
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seg->trbs, (unsigned long long)seg->dma);
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dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
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seg->trbs = NULL;
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}
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xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
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kfree(seg);
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}
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/*
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* Make the prev segment point to the next segment.
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*
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* Change the last TRB in the prev segment to be a Link TRB which points to the
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* DMA address of the next segment. The caller needs to set any Link TRB
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* related flags, such as End TRB, Toggle Cycle, and no snoop.
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*/
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static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
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struct xhci_segment *next, bool link_trbs)
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{
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u32 val;
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if (!prev || !next)
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return;
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prev->next = next;
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if (link_trbs) {
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prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma;
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/* Set the last TRB in the segment to have a TRB type ID of Link TRB */
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val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
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val &= ~TRB_TYPE_BITMASK;
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val |= TRB_TYPE(TRB_LINK);
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prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
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}
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xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
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(unsigned long long)prev->dma,
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(unsigned long long)next->dma);
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}
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/* XXX: Do we need the hcd structure in all these functions? */
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void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
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{
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struct xhci_segment *seg;
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struct xhci_segment *first_seg;
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if (!ring || !ring->first_seg)
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return;
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first_seg = ring->first_seg;
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seg = first_seg->next;
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xhci_dbg(xhci, "Freeing ring at %p\n", ring);
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while (seg != first_seg) {
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struct xhci_segment *next = seg->next;
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xhci_segment_free(xhci, seg);
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seg = next;
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}
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xhci_segment_free(xhci, first_seg);
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ring->first_seg = NULL;
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kfree(ring);
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}
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/**
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* Create a new ring with zero or more segments.
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*
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* Link each segment together into a ring.
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* Set the end flag and the cycle toggle bit on the last segment.
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* See section 4.9.1 and figures 15 and 16.
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*/
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static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
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unsigned int num_segs, bool link_trbs, gfp_t flags)
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{
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struct xhci_ring *ring;
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struct xhci_segment *prev;
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ring = kzalloc(sizeof *(ring), flags);
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xhci_dbg(xhci, "Allocating ring at %p\n", ring);
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if (!ring)
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return 0;
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INIT_LIST_HEAD(&ring->td_list);
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INIT_LIST_HEAD(&ring->cancelled_td_list);
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if (num_segs == 0)
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return ring;
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ring->first_seg = xhci_segment_alloc(xhci, flags);
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if (!ring->first_seg)
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goto fail;
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num_segs--;
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prev = ring->first_seg;
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while (num_segs > 0) {
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struct xhci_segment *next;
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next = xhci_segment_alloc(xhci, flags);
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if (!next)
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goto fail;
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xhci_link_segments(xhci, prev, next, link_trbs);
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prev = next;
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num_segs--;
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}
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xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
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if (link_trbs) {
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/* See section 4.9.2.1 and 6.4.4.1 */
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prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
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xhci_dbg(xhci, "Wrote link toggle flag to"
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" segment %p (virtual), 0x%llx (DMA)\n",
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prev, (unsigned long long)prev->dma);
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}
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/* The ring is empty, so the enqueue pointer == dequeue pointer */
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ring->enqueue = ring->first_seg->trbs;
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ring->enq_seg = ring->first_seg;
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ring->dequeue = ring->enqueue;
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ring->deq_seg = ring->first_seg;
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/* The ring is initialized to 0. The producer must write 1 to the cycle
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* bit to handover ownership of the TRB, so PCS = 1. The consumer must
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* compare CCS to the cycle bit to check ownership, so CCS = 1.
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*/
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ring->cycle_state = 1;
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return ring;
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fail:
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xhci_ring_free(xhci, ring);
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return 0;
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}
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#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
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struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
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int type, gfp_t flags)
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{
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struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
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if (!ctx)
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return NULL;
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BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
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ctx->type = type;
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ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
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if (type == XHCI_CTX_TYPE_INPUT)
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ctx->size += CTX_SIZE(xhci->hcc_params);
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ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
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memset(ctx->bytes, 0, ctx->size);
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return ctx;
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}
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void xhci_free_container_ctx(struct xhci_hcd *xhci,
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struct xhci_container_ctx *ctx)
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{
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dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
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kfree(ctx);
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}
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struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
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struct xhci_container_ctx *ctx)
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{
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BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
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return (struct xhci_input_control_ctx *)ctx->bytes;
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}
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struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
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struct xhci_container_ctx *ctx)
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{
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if (ctx->type == XHCI_CTX_TYPE_DEVICE)
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return (struct xhci_slot_ctx *)ctx->bytes;
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return (struct xhci_slot_ctx *)
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(ctx->bytes + CTX_SIZE(xhci->hcc_params));
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}
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struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
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struct xhci_container_ctx *ctx,
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unsigned int ep_index)
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{
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/* increment ep index by offset of start of ep ctx array */
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ep_index++;
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if (ctx->type == XHCI_CTX_TYPE_INPUT)
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ep_index++;
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return (struct xhci_ep_ctx *)
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(ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
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}
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/* All the xhci_tds in the ring's TD list should be freed at this point */
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void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
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{
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struct xhci_virt_device *dev;
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int i;
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/* Slot ID 0 is reserved */
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if (slot_id == 0 || !xhci->devs[slot_id])
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return;
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dev = xhci->devs[slot_id];
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xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
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if (!dev)
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return;
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for (i = 0; i < 31; ++i)
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if (dev->ep_rings[i])
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xhci_ring_free(xhci, dev->ep_rings[i]);
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if (dev->in_ctx)
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xhci_free_container_ctx(xhci, dev->in_ctx);
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if (dev->out_ctx)
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xhci_free_container_ctx(xhci, dev->out_ctx);
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kfree(xhci->devs[slot_id]);
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xhci->devs[slot_id] = 0;
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}
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int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
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struct usb_device *udev, gfp_t flags)
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{
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struct xhci_virt_device *dev;
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/* Slot ID 0 is reserved */
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if (slot_id == 0 || xhci->devs[slot_id]) {
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xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
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return 0;
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}
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xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
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if (!xhci->devs[slot_id])
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return 0;
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dev = xhci->devs[slot_id];
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/* Allocate the (output) device context that will be used in the HC. */
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dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
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if (!dev->out_ctx)
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goto fail;
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xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
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(unsigned long long)dev->out_ctx->dma);
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/* Allocate the (input) device context for address device command */
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dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
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if (!dev->in_ctx)
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goto fail;
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xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
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(unsigned long long)dev->in_ctx->dma);
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/* Allocate endpoint 0 ring */
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dev->ep_rings[0] = xhci_ring_alloc(xhci, 1, true, flags);
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if (!dev->ep_rings[0])
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goto fail;
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init_completion(&dev->cmd_completion);
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/* Point to output device context in dcbaa. */
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xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;
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xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
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slot_id,
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&xhci->dcbaa->dev_context_ptrs[slot_id],
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(unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);
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return 1;
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fail:
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xhci_free_virt_device(xhci, slot_id);
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return 0;
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}
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/* Setup an xHCI virtual device for a Set Address command */
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int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
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{
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struct xhci_virt_device *dev;
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struct xhci_ep_ctx *ep0_ctx;
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struct usb_device *top_dev;
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struct xhci_slot_ctx *slot_ctx;
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struct xhci_input_control_ctx *ctrl_ctx;
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dev = xhci->devs[udev->slot_id];
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/* Slot ID 0 is reserved */
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if (udev->slot_id == 0 || !dev) {
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xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
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udev->slot_id);
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return -EINVAL;
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}
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ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
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ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
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slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
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/* 2) New slot context and endpoint 0 context are valid*/
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ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
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/* 3) Only the control endpoint is valid - one endpoint context */
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slot_ctx->dev_info |= LAST_CTX(1);
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switch (udev->speed) {
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case USB_SPEED_SUPER:
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slot_ctx->dev_info |= (u32) udev->route;
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slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;
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break;
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case USB_SPEED_HIGH:
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slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;
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break;
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case USB_SPEED_FULL:
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slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;
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break;
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case USB_SPEED_LOW:
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slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;
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break;
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case USB_SPEED_VARIABLE:
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xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
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return -EINVAL;
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break;
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default:
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/* Speed was set earlier, this shouldn't happen. */
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BUG();
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}
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/* Find the root hub port this device is under */
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for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
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top_dev = top_dev->parent)
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/* Found device below root hub */;
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slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
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xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
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|
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/* Is this a LS/FS device under a HS hub? */
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/*
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* FIXME: I don't think this is right, where does the TT info for the
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* roothub or parent hub come from?
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*/
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if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
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udev->tt) {
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slot_ctx->tt_info = udev->tt->hub->slot_id;
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slot_ctx->tt_info |= udev->ttport << 8;
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}
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xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
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xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
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|
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/* Step 4 - ring already allocated */
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/* Step 5 */
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ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
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/*
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* See section 4.3 bullet 6:
|
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* The default Max Packet size for ep0 is "8 bytes for a USB2
|
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* LS/FS/HS device or 512 bytes for a USB3 SS device"
|
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* XXX: Not sure about wireless USB devices.
|
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*/
|
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if (udev->speed == USB_SPEED_SUPER)
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ep0_ctx->ep_info2 |= MAX_PACKET(512);
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else
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ep0_ctx->ep_info2 |= MAX_PACKET(8);
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/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
|
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ep0_ctx->ep_info2 |= MAX_BURST(0);
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ep0_ctx->ep_info2 |= ERROR_COUNT(3);
|
|
|
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ep0_ctx->deq =
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dev->ep_rings[0]->first_seg->dma;
|
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ep0_ctx->deq |= dev->ep_rings[0]->cycle_state;
|
|
|
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/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
|
|
|
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return 0;
|
|
}
|
|
|
|
/* Return the polling or NAK interval.
|
|
*
|
|
* The polling interval is expressed in "microframes". If xHCI's Interval field
|
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* is set to N, it will service the endpoint every 2^(Interval)*125us.
|
|
*
|
|
* The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
|
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* is set to 0.
|
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*/
|
|
static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
|
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struct usb_host_endpoint *ep)
|
|
{
|
|
unsigned int interval = 0;
|
|
|
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switch (udev->speed) {
|
|
case USB_SPEED_HIGH:
|
|
/* Max NAK rate */
|
|
if (usb_endpoint_xfer_control(&ep->desc) ||
|
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usb_endpoint_xfer_bulk(&ep->desc))
|
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interval = ep->desc.bInterval;
|
|
/* Fall through - SS and HS isoc/int have same decoding */
|
|
case USB_SPEED_SUPER:
|
|
if (usb_endpoint_xfer_int(&ep->desc) ||
|
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usb_endpoint_xfer_isoc(&ep->desc)) {
|
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if (ep->desc.bInterval == 0)
|
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interval = 0;
|
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else
|
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interval = ep->desc.bInterval - 1;
|
|
if (interval > 15)
|
|
interval = 15;
|
|
if (interval != ep->desc.bInterval + 1)
|
|
dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
|
|
ep->desc.bEndpointAddress, 1 << interval);
|
|
}
|
|
break;
|
|
/* Convert bInterval (in 1-255 frames) to microframes and round down to
|
|
* nearest power of 2.
|
|
*/
|
|
case USB_SPEED_FULL:
|
|
case USB_SPEED_LOW:
|
|
if (usb_endpoint_xfer_int(&ep->desc) ||
|
|
usb_endpoint_xfer_isoc(&ep->desc)) {
|
|
interval = fls(8*ep->desc.bInterval) - 1;
|
|
if (interval > 10)
|
|
interval = 10;
|
|
if (interval < 3)
|
|
interval = 3;
|
|
if ((1 << interval) != 8*ep->desc.bInterval)
|
|
dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
|
|
ep->desc.bEndpointAddress, 1 << interval);
|
|
}
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
return EP_INTERVAL(interval);
|
|
}
|
|
|
|
static inline u32 xhci_get_endpoint_type(struct usb_device *udev,
|
|
struct usb_host_endpoint *ep)
|
|
{
|
|
int in;
|
|
u32 type;
|
|
|
|
in = usb_endpoint_dir_in(&ep->desc);
|
|
if (usb_endpoint_xfer_control(&ep->desc)) {
|
|
type = EP_TYPE(CTRL_EP);
|
|
} else if (usb_endpoint_xfer_bulk(&ep->desc)) {
|
|
if (in)
|
|
type = EP_TYPE(BULK_IN_EP);
|
|
else
|
|
type = EP_TYPE(BULK_OUT_EP);
|
|
} else if (usb_endpoint_xfer_isoc(&ep->desc)) {
|
|
if (in)
|
|
type = EP_TYPE(ISOC_IN_EP);
|
|
else
|
|
type = EP_TYPE(ISOC_OUT_EP);
|
|
} else if (usb_endpoint_xfer_int(&ep->desc)) {
|
|
if (in)
|
|
type = EP_TYPE(INT_IN_EP);
|
|
else
|
|
type = EP_TYPE(INT_OUT_EP);
|
|
} else {
|
|
BUG();
|
|
}
|
|
return type;
|
|
}
|
|
|
|
int xhci_endpoint_init(struct xhci_hcd *xhci,
|
|
struct xhci_virt_device *virt_dev,
|
|
struct usb_device *udev,
|
|
struct usb_host_endpoint *ep,
|
|
gfp_t mem_flags)
|
|
{
|
|
unsigned int ep_index;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
struct xhci_ring *ep_ring;
|
|
unsigned int max_packet;
|
|
unsigned int max_burst;
|
|
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
|
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
|
|
|
|
/* Set up the endpoint ring */
|
|
virt_dev->new_ep_rings[ep_index] = xhci_ring_alloc(xhci, 1, true, mem_flags);
|
|
if (!virt_dev->new_ep_rings[ep_index])
|
|
return -ENOMEM;
|
|
ep_ring = virt_dev->new_ep_rings[ep_index];
|
|
ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
|
|
|
|
ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
|
|
|
|
/* FIXME dig Mult and streams info out of ep companion desc */
|
|
|
|
/* Allow 3 retries for everything but isoc;
|
|
* error count = 0 means infinite retries.
|
|
*/
|
|
if (!usb_endpoint_xfer_isoc(&ep->desc))
|
|
ep_ctx->ep_info2 = ERROR_COUNT(3);
|
|
else
|
|
ep_ctx->ep_info2 = ERROR_COUNT(1);
|
|
|
|
ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
|
|
|
|
/* Set the max packet size and max burst */
|
|
switch (udev->speed) {
|
|
case USB_SPEED_SUPER:
|
|
max_packet = ep->desc.wMaxPacketSize;
|
|
ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
|
|
/* dig out max burst from ep companion desc */
|
|
if (!ep->ss_ep_comp) {
|
|
xhci_warn(xhci, "WARN no SS endpoint companion descriptor.\n");
|
|
max_packet = 0;
|
|
} else {
|
|
max_packet = ep->ss_ep_comp->desc.bMaxBurst;
|
|
}
|
|
ep_ctx->ep_info2 |= MAX_BURST(max_packet);
|
|
break;
|
|
case USB_SPEED_HIGH:
|
|
/* bits 11:12 specify the number of additional transaction
|
|
* opportunities per microframe (USB 2.0, section 9.6.6)
|
|
*/
|
|
if (usb_endpoint_xfer_isoc(&ep->desc) ||
|
|
usb_endpoint_xfer_int(&ep->desc)) {
|
|
max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
|
|
ep_ctx->ep_info2 |= MAX_BURST(max_burst);
|
|
}
|
|
/* Fall through */
|
|
case USB_SPEED_FULL:
|
|
case USB_SPEED_LOW:
|
|
max_packet = ep->desc.wMaxPacketSize & 0x3ff;
|
|
ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
/* FIXME Debug endpoint context */
|
|
return 0;
|
|
}
|
|
|
|
void xhci_endpoint_zero(struct xhci_hcd *xhci,
|
|
struct xhci_virt_device *virt_dev,
|
|
struct usb_host_endpoint *ep)
|
|
{
|
|
unsigned int ep_index;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
|
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
|
|
|
|
ep_ctx->ep_info = 0;
|
|
ep_ctx->ep_info2 = 0;
|
|
ep_ctx->deq = 0;
|
|
ep_ctx->tx_info = 0;
|
|
/* Don't free the endpoint ring until the set interface or configuration
|
|
* request succeeds.
|
|
*/
|
|
}
|
|
|
|
/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
|
|
static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
|
|
{
|
|
int i;
|
|
struct device *dev = xhci_to_hcd(xhci)->self.controller;
|
|
int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
|
|
|
|
xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
|
|
|
|
if (!num_sp)
|
|
return 0;
|
|
|
|
xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
|
|
if (!xhci->scratchpad)
|
|
goto fail_sp;
|
|
|
|
xhci->scratchpad->sp_array =
|
|
pci_alloc_consistent(to_pci_dev(dev),
|
|
num_sp * sizeof(u64),
|
|
&xhci->scratchpad->sp_dma);
|
|
if (!xhci->scratchpad->sp_array)
|
|
goto fail_sp2;
|
|
|
|
xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
|
|
if (!xhci->scratchpad->sp_buffers)
|
|
goto fail_sp3;
|
|
|
|
xhci->scratchpad->sp_dma_buffers =
|
|
kzalloc(sizeof(dma_addr_t) * num_sp, flags);
|
|
|
|
if (!xhci->scratchpad->sp_dma_buffers)
|
|
goto fail_sp4;
|
|
|
|
xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma;
|
|
for (i = 0; i < num_sp; i++) {
|
|
dma_addr_t dma;
|
|
void *buf = pci_alloc_consistent(to_pci_dev(dev),
|
|
xhci->page_size, &dma);
|
|
if (!buf)
|
|
goto fail_sp5;
|
|
|
|
xhci->scratchpad->sp_array[i] = dma;
|
|
xhci->scratchpad->sp_buffers[i] = buf;
|
|
xhci->scratchpad->sp_dma_buffers[i] = dma;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_sp5:
|
|
for (i = i - 1; i >= 0; i--) {
|
|
pci_free_consistent(to_pci_dev(dev), xhci->page_size,
|
|
xhci->scratchpad->sp_buffers[i],
|
|
xhci->scratchpad->sp_dma_buffers[i]);
|
|
}
|
|
kfree(xhci->scratchpad->sp_dma_buffers);
|
|
|
|
fail_sp4:
|
|
kfree(xhci->scratchpad->sp_buffers);
|
|
|
|
fail_sp3:
|
|
pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
|
|
xhci->scratchpad->sp_array,
|
|
xhci->scratchpad->sp_dma);
|
|
|
|
fail_sp2:
|
|
kfree(xhci->scratchpad);
|
|
xhci->scratchpad = NULL;
|
|
|
|
fail_sp:
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void scratchpad_free(struct xhci_hcd *xhci)
|
|
{
|
|
int num_sp;
|
|
int i;
|
|
struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
|
|
|
|
if (!xhci->scratchpad)
|
|
return;
|
|
|
|
num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
|
|
|
|
for (i = 0; i < num_sp; i++) {
|
|
pci_free_consistent(pdev, xhci->page_size,
|
|
xhci->scratchpad->sp_buffers[i],
|
|
xhci->scratchpad->sp_dma_buffers[i]);
|
|
}
|
|
kfree(xhci->scratchpad->sp_dma_buffers);
|
|
kfree(xhci->scratchpad->sp_buffers);
|
|
pci_free_consistent(pdev, num_sp * sizeof(u64),
|
|
xhci->scratchpad->sp_array,
|
|
xhci->scratchpad->sp_dma);
|
|
kfree(xhci->scratchpad);
|
|
xhci->scratchpad = NULL;
|
|
}
|
|
|
|
void xhci_mem_cleanup(struct xhci_hcd *xhci)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
|
|
int size;
|
|
int i;
|
|
|
|
/* Free the Event Ring Segment Table and the actual Event Ring */
|
|
xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
|
|
xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
|
|
xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
|
|
size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
|
|
if (xhci->erst.entries)
|
|
pci_free_consistent(pdev, size,
|
|
xhci->erst.entries, xhci->erst.erst_dma_addr);
|
|
xhci->erst.entries = NULL;
|
|
xhci_dbg(xhci, "Freed ERST\n");
|
|
if (xhci->event_ring)
|
|
xhci_ring_free(xhci, xhci->event_ring);
|
|
xhci->event_ring = NULL;
|
|
xhci_dbg(xhci, "Freed event ring\n");
|
|
|
|
xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
|
|
if (xhci->cmd_ring)
|
|
xhci_ring_free(xhci, xhci->cmd_ring);
|
|
xhci->cmd_ring = NULL;
|
|
xhci_dbg(xhci, "Freed command ring\n");
|
|
|
|
for (i = 1; i < MAX_HC_SLOTS; ++i)
|
|
xhci_free_virt_device(xhci, i);
|
|
|
|
if (xhci->segment_pool)
|
|
dma_pool_destroy(xhci->segment_pool);
|
|
xhci->segment_pool = NULL;
|
|
xhci_dbg(xhci, "Freed segment pool\n");
|
|
|
|
if (xhci->device_pool)
|
|
dma_pool_destroy(xhci->device_pool);
|
|
xhci->device_pool = NULL;
|
|
xhci_dbg(xhci, "Freed device context pool\n");
|
|
|
|
xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
|
|
if (xhci->dcbaa)
|
|
pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
|
|
xhci->dcbaa, xhci->dcbaa->dma);
|
|
xhci->dcbaa = NULL;
|
|
|
|
xhci->page_size = 0;
|
|
xhci->page_shift = 0;
|
|
scratchpad_free(xhci);
|
|
}
|
|
|
|
int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
|
|
{
|
|
dma_addr_t dma;
|
|
struct device *dev = xhci_to_hcd(xhci)->self.controller;
|
|
unsigned int val, val2;
|
|
u64 val_64;
|
|
struct xhci_segment *seg;
|
|
u32 page_size;
|
|
int i;
|
|
|
|
page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
|
|
xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
|
|
for (i = 0; i < 16; i++) {
|
|
if ((0x1 & page_size) != 0)
|
|
break;
|
|
page_size = page_size >> 1;
|
|
}
|
|
if (i < 16)
|
|
xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
|
|
else
|
|
xhci_warn(xhci, "WARN: no supported page size\n");
|
|
/* Use 4K pages, since that's common and the minimum the HC supports */
|
|
xhci->page_shift = 12;
|
|
xhci->page_size = 1 << xhci->page_shift;
|
|
xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
|
|
|
|
/*
|
|
* Program the Number of Device Slots Enabled field in the CONFIG
|
|
* register with the max value of slots the HC can handle.
|
|
*/
|
|
val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
|
|
xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
|
|
(unsigned int) val);
|
|
val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
|
|
val |= (val2 & ~HCS_SLOTS_MASK);
|
|
xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
|
|
(unsigned int) val);
|
|
xhci_writel(xhci, val, &xhci->op_regs->config_reg);
|
|
|
|
/*
|
|
* Section 5.4.8 - doorbell array must be
|
|
* "physically contiguous and 64-byte (cache line) aligned".
|
|
*/
|
|
xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
|
|
sizeof(*xhci->dcbaa), &dma);
|
|
if (!xhci->dcbaa)
|
|
goto fail;
|
|
memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
|
|
xhci->dcbaa->dma = dma;
|
|
xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
|
|
(unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
|
|
xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
|
|
|
|
/*
|
|
* Initialize the ring segment pool. The ring must be a contiguous
|
|
* structure comprised of TRBs. The TRBs must be 16 byte aligned,
|
|
* however, the command ring segment needs 64-byte aligned segments,
|
|
* so we pick the greater alignment need.
|
|
*/
|
|
xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
|
|
SEGMENT_SIZE, 64, xhci->page_size);
|
|
|
|
/* See Table 46 and Note on Figure 55 */
|
|
xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
|
|
2112, 64, xhci->page_size);
|
|
if (!xhci->segment_pool || !xhci->device_pool)
|
|
goto fail;
|
|
|
|
/* Set up the command ring to have one segments for now. */
|
|
xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
|
|
if (!xhci->cmd_ring)
|
|
goto fail;
|
|
xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
|
|
xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
|
|
(unsigned long long)xhci->cmd_ring->first_seg->dma);
|
|
|
|
/* Set the address in the Command Ring Control register */
|
|
val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
|
val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
|
|
(xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
|
|
xhci->cmd_ring->cycle_state;
|
|
xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
|
|
xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
|
|
xhci_dbg_cmd_ptrs(xhci);
|
|
|
|
val = xhci_readl(xhci, &xhci->cap_regs->db_off);
|
|
val &= DBOFF_MASK;
|
|
xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
|
|
" from cap regs base addr\n", val);
|
|
xhci->dba = (void *) xhci->cap_regs + val;
|
|
xhci_dbg_regs(xhci);
|
|
xhci_print_run_regs(xhci);
|
|
/* Set ir_set to interrupt register set 0 */
|
|
xhci->ir_set = (void *) xhci->run_regs->ir_set;
|
|
|
|
/*
|
|
* Event ring setup: Allocate a normal ring, but also setup
|
|
* the event ring segment table (ERST). Section 4.9.3.
|
|
*/
|
|
xhci_dbg(xhci, "// Allocating event ring\n");
|
|
xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
|
|
if (!xhci->event_ring)
|
|
goto fail;
|
|
|
|
xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
|
|
sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
|
|
if (!xhci->erst.entries)
|
|
goto fail;
|
|
xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
|
|
(unsigned long long)dma);
|
|
|
|
memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
|
|
xhci->erst.num_entries = ERST_NUM_SEGS;
|
|
xhci->erst.erst_dma_addr = dma;
|
|
xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
|
|
xhci->erst.num_entries,
|
|
xhci->erst.entries,
|
|
(unsigned long long)xhci->erst.erst_dma_addr);
|
|
|
|
/* set ring base address and size for each segment table entry */
|
|
for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
|
|
struct xhci_erst_entry *entry = &xhci->erst.entries[val];
|
|
entry->seg_addr = seg->dma;
|
|
entry->seg_size = TRBS_PER_SEGMENT;
|
|
entry->rsvd = 0;
|
|
seg = seg->next;
|
|
}
|
|
|
|
/* set ERST count with the number of entries in the segment table */
|
|
val = xhci_readl(xhci, &xhci->ir_set->erst_size);
|
|
val &= ERST_SIZE_MASK;
|
|
val |= ERST_NUM_SEGS;
|
|
xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
|
|
val);
|
|
xhci_writel(xhci, val, &xhci->ir_set->erst_size);
|
|
|
|
xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
|
|
/* set the segment table base address */
|
|
xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
|
|
(unsigned long long)xhci->erst.erst_dma_addr);
|
|
val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
|
|
val_64 &= ERST_PTR_MASK;
|
|
val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
|
|
xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
|
|
|
|
/* Set the event ring dequeue address */
|
|
xhci_set_hc_event_deq(xhci);
|
|
xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
|
|
xhci_print_ir_set(xhci, xhci->ir_set, 0);
|
|
|
|
/*
|
|
* XXX: Might need to set the Interrupter Moderation Register to
|
|
* something other than the default (~1ms minimum between interrupts).
|
|
* See section 5.5.1.2.
|
|
*/
|
|
init_completion(&xhci->addr_dev);
|
|
for (i = 0; i < MAX_HC_SLOTS; ++i)
|
|
xhci->devs[i] = 0;
|
|
|
|
if (scratchpad_alloc(xhci, flags))
|
|
goto fail;
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
xhci_warn(xhci, "Couldn't initialize memory\n");
|
|
xhci_mem_cleanup(xhci);
|
|
return -ENOMEM;
|
|
}
|