42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
== Introduction==
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LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
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that can be shared by multiple clients. Clients here are different cores in the
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SOC, the idea is to minimize the local caches at the clients and migrate to
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common pool of memory. Cache memory is divided into partitions called slices
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which are assigned to clients. Clients can query the slice details, activate
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and deactivate them.
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Properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be "qcom,sdm845-llcc"
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- reg:
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Usage: required
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Value Type: <prop-encoded-array>
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Definition: The first element specifies the llcc base start address and
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the size of the register region. The second element specifies
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the llcc broadcast base address and size of the register region.
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- reg-names:
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Usage: required
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Value Type: <stringlist>
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Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".
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- interrupts:
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Usage: required
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Definition: The interrupt is associated with the llcc edac device.
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It's used for llcc cache single and double bit error detection
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and reporting.
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Example:
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cache-controller@1100000 {
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compatible = "qcom,sdm845-llcc";
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reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
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reg-names = "llcc_base", "llcc_broadcast_base";
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interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
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};
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