273 lines
6.3 KiB
C
273 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Hi6220 stub clock driver
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*
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* Copyright (c) 2015 Hisilicon Limited.
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* Copyright (c) 2015 Linaro Limited.
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*
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* Author: Leo Yan <leo.yan@linaro.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mailbox_client.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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/* Stub clocks id */
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#define HI6220_STUB_ACPU0 0
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#define HI6220_STUB_ACPU1 1
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#define HI6220_STUB_GPU 2
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#define HI6220_STUB_DDR 5
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/* Mailbox message */
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#define HI6220_MBOX_MSG_LEN 8
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#define HI6220_MBOX_FREQ 0xA
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#define HI6220_MBOX_CMD_SET 0x3
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#define HI6220_MBOX_OBJ_AP 0x0
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/* CPU dynamic frequency scaling */
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#define ACPU_DFS_FREQ_MAX 0x1724
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#define ACPU_DFS_CUR_FREQ 0x17CC
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#define ACPU_DFS_FLAG 0x1B30
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#define ACPU_DFS_FREQ_REQ 0x1B34
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#define ACPU_DFS_FREQ_LMT 0x1B38
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#define ACPU_DFS_LOCK_FLAG 0xAEAEAEAE
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#define to_stub_clk(hw) container_of(hw, struct hi6220_stub_clk, hw)
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struct hi6220_stub_clk {
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u32 id;
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struct device *dev;
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struct clk_hw hw;
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struct regmap *dfs_map;
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struct mbox_client cl;
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struct mbox_chan *mbox;
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};
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struct hi6220_mbox_msg {
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unsigned char type;
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unsigned char cmd;
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unsigned char obj;
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unsigned char src;
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unsigned char para[4];
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};
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union hi6220_mbox_data {
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unsigned int data[HI6220_MBOX_MSG_LEN];
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struct hi6220_mbox_msg msg;
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};
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static unsigned int hi6220_acpu_get_freq(struct hi6220_stub_clk *stub_clk)
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{
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unsigned int freq;
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regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq);
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return freq;
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}
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static int hi6220_acpu_set_freq(struct hi6220_stub_clk *stub_clk,
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unsigned int freq)
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{
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union hi6220_mbox_data data;
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/* set the frequency in sram */
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regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq);
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/* compound mailbox message */
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data.msg.type = HI6220_MBOX_FREQ;
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data.msg.cmd = HI6220_MBOX_CMD_SET;
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data.msg.obj = HI6220_MBOX_OBJ_AP;
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data.msg.src = HI6220_MBOX_OBJ_AP;
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mbox_send_message(stub_clk->mbox, &data);
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return 0;
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}
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static int hi6220_acpu_round_freq(struct hi6220_stub_clk *stub_clk,
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unsigned int freq)
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{
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unsigned int limit_flag, limit_freq = UINT_MAX;
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unsigned int max_freq;
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/* check the constrained frequency */
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regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag);
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if (limit_flag == ACPU_DFS_LOCK_FLAG)
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regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq);
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/* check the supported maximum frequency */
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regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq);
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/* calculate the real maximum frequency */
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max_freq = min(max_freq, limit_freq);
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if (WARN_ON(freq > max_freq))
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freq = max_freq;
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return freq;
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}
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static unsigned long hi6220_stub_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 rate = 0;
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struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
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switch (stub_clk->id) {
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case HI6220_STUB_ACPU0:
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rate = hi6220_acpu_get_freq(stub_clk);
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/* convert from kHz to Hz */
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rate *= 1000;
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break;
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default:
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dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
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__func__, stub_clk->id);
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break;
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}
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return rate;
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}
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static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
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unsigned long new_rate = rate / 1000; /* kHz */
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int ret = 0;
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switch (stub_clk->id) {
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case HI6220_STUB_ACPU0:
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ret = hi6220_acpu_set_freq(stub_clk, new_rate);
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if (ret < 0)
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return ret;
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break;
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default:
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dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
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__func__, stub_clk->id);
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break;
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}
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pr_debug("%s: set rate=%ldkHz\n", __func__, new_rate);
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return ret;
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}
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static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
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unsigned long new_rate = rate / 1000; /* kHz */
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switch (stub_clk->id) {
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case HI6220_STUB_ACPU0:
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new_rate = hi6220_acpu_round_freq(stub_clk, new_rate);
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/* convert from kHz to Hz */
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new_rate *= 1000;
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break;
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default:
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dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
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__func__, stub_clk->id);
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break;
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}
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return new_rate;
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}
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static const struct clk_ops hi6220_stub_clk_ops = {
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.recalc_rate = hi6220_stub_clk_recalc_rate,
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.round_rate = hi6220_stub_clk_round_rate,
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.set_rate = hi6220_stub_clk_set_rate,
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};
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static int hi6220_stub_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct clk_init_data init;
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struct hi6220_stub_clk *stub_clk;
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struct clk *clk;
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struct device_node *np = pdev->dev.of_node;
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int ret;
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stub_clk = devm_kzalloc(dev, sizeof(*stub_clk), GFP_KERNEL);
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if (!stub_clk)
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return -ENOMEM;
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stub_clk->dfs_map = syscon_regmap_lookup_by_phandle(np,
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"hisilicon,hi6220-clk-sram");
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if (IS_ERR(stub_clk->dfs_map)) {
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dev_err(dev, "failed to get sram regmap\n");
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return PTR_ERR(stub_clk->dfs_map);
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}
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stub_clk->hw.init = &init;
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stub_clk->dev = dev;
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stub_clk->id = HI6220_STUB_ACPU0;
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/* Use mailbox client with blocking mode */
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stub_clk->cl.dev = dev;
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stub_clk->cl.tx_done = NULL;
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stub_clk->cl.tx_block = true;
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stub_clk->cl.tx_tout = 500;
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stub_clk->cl.knows_txdone = false;
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/* Allocate mailbox channel */
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stub_clk->mbox = mbox_request_channel(&stub_clk->cl, 0);
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if (IS_ERR(stub_clk->mbox)) {
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dev_err(dev, "failed get mailbox channel\n");
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return PTR_ERR(stub_clk->mbox);
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}
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init.name = "acpu0";
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init.ops = &hi6220_stub_clk_ops;
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init.num_parents = 0;
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init.flags = 0;
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clk = devm_clk_register(dev, &stub_clk->hw);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
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if (ret) {
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dev_err(dev, "failed to register OF clock provider\n");
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return ret;
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}
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/* initialize buffer to zero */
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regmap_write(stub_clk->dfs_map, ACPU_DFS_FLAG, 0x0);
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regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, 0x0);
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regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, 0x0);
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dev_dbg(dev, "Registered clock '%s'\n", init.name);
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return 0;
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}
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static const struct of_device_id hi6220_stub_clk_of_match[] = {
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{ .compatible = "hisilicon,hi6220-stub-clk", },
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{}
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};
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static struct platform_driver hi6220_stub_clk_driver = {
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.driver = {
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.name = "hi6220-stub-clk",
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.of_match_table = hi6220_stub_clk_of_match,
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},
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.probe = hi6220_stub_clk_probe,
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};
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static int __init hi6220_stub_clk_init(void)
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{
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return platform_driver_register(&hi6220_stub_clk_driver);
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}
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subsys_initcall(hi6220_stub_clk_init);
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