228 lines
6.2 KiB
C
228 lines
6.2 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SI_DPM_H__
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#define __SI_DPM_H__
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#include "ni_dpm.h"
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#include "sislands_smc.h"
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enum si_cac_config_reg_type
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{
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SISLANDS_CACCONFIG_MMR = 0,
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SISLANDS_CACCONFIG_CGIND,
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SISLANDS_CACCONFIG_MAX
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};
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struct si_cac_config_reg
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{
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u32 offset;
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u32 mask;
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u32 shift;
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u32 value;
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enum si_cac_config_reg_type type;
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};
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struct si_powertune_data
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{
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u32 cac_window;
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u32 l2_lta_window_size_default;
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u8 lts_truncate_default;
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u8 shift_n_default;
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u8 operating_temp;
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struct ni_leakage_coeffients leakage_coefficients;
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u32 fixed_kt;
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u32 lkge_lut_v0_percent;
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u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
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bool enable_powertune_by_default;
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};
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struct si_dyn_powertune_data
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{
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u32 cac_leakage;
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s32 leakage_minimum_temperature;
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u32 wintime;
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u32 l2_lta_window_size;
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u8 lts_truncate;
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u8 shift_n;
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u8 dc_pwr_value;
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bool disable_uvd_powertune;
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};
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struct si_dte_data
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{
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u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
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u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];
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u32 k;
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u32 t0;
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u32 max_t;
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u8 window_size;
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u8 temp_select;
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u8 dte_mode;
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u8 tdep_count;
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u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
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u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
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u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];
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u32 t_threshold;
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bool enable_dte_by_default;
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};
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struct si_clock_registers {
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u32 cg_spll_func_cntl;
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u32 cg_spll_func_cntl_2;
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u32 cg_spll_func_cntl_3;
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u32 cg_spll_func_cntl_4;
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u32 cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2;
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u32 dll_cntl;
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u32 mclk_pwrmgt_cntl;
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u32 mpll_ad_func_cntl;
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u32 mpll_dq_func_cntl;
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u32 mpll_func_cntl;
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u32 mpll_func_cntl_1;
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u32 mpll_func_cntl_2;
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u32 mpll_ss1;
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u32 mpll_ss2;
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};
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struct si_mc_reg_entry {
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u32 mclk_max;
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u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
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};
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struct si_mc_reg_table {
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u8 last;
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u8 num_entries;
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u16 valid_flag;
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struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
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SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];
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};
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#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0
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#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1
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#define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2
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#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3
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struct si_leakage_voltage_entry
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{
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u16 voltage;
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u16 leakage_index;
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};
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#define SISLANDS_LEAKAGE_INDEX0 0xff01
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#define SISLANDS_MAX_LEAKAGE_COUNT 4
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struct si_leakage_voltage
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{
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u16 count;
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struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];
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};
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#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5
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struct si_ulv_param {
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bool supported;
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u32 cg_ulv_control;
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u32 cg_ulv_parameter;
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u32 volt_change_delay;
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struct rv7xx_pl pl;
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bool one_pcie_lane_in_ulv;
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};
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struct si_power_info {
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/* must be first! */
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struct ni_power_info ni;
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struct si_clock_registers clock_registers;
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struct si_mc_reg_table mc_reg_table;
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struct atom_voltage_table mvdd_voltage_table;
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struct atom_voltage_table vddc_phase_shed_table;
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struct si_leakage_voltage leakage_voltage;
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u16 mvdd_bootup_value;
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struct si_ulv_param ulv;
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u32 max_cu;
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/* pcie gen */
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enum radeon_pcie_gen force_pcie_gen;
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enum radeon_pcie_gen boot_pcie_gen;
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enum radeon_pcie_gen acpi_pcie_gen;
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u32 sys_pcie_mask;
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/* flags */
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bool enable_dte;
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bool enable_ppm;
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bool vddc_phase_shed_control;
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bool pspp_notify_required;
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bool sclk_deep_sleep_above_low;
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/* smc offsets */
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u32 sram_end;
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u32 state_table_start;
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u32 soft_regs_start;
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u32 mc_reg_table_start;
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u32 arb_table_start;
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u32 cac_table_start;
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u32 dte_table_start;
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u32 spll_table_start;
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u32 papm_cfg_table_start;
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/* CAC stuff */
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const struct si_cac_config_reg *cac_weights;
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const struct si_cac_config_reg *lcac_config;
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const struct si_cac_config_reg *cac_override;
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const struct si_powertune_data *powertune_data;
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struct si_dyn_powertune_data dyn_powertune_data;
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/* DTE stuff */
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struct si_dte_data dte_data;
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/* scratch structs */
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SMC_SIslands_MCRegisters smc_mc_reg_table;
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SISLANDS_SMC_STATETABLE smc_statetable;
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PP_SIslands_PAPMParameters papm_parm;
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};
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#define SISLANDS_INITIAL_STATE_ARB_INDEX 0
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#define SISLANDS_ACPI_STATE_ARB_INDEX 1
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#define SISLANDS_ULV_STATE_ARB_INDEX 2
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#define SISLANDS_DRIVER_STATE_ARB_INDEX 3
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#define SISLANDS_DPM2_MAX_PULSE_SKIP 256
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#define SISLANDS_DPM2_NEAR_TDP_DEC 10
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#define SISLANDS_DPM2_ABOVE_SAFE_INC 5
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#define SISLANDS_DPM2_BELOW_SAFE_INC 20
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#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80
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#define SISLANDS_DPM2_MAXPS_PERCENT_H 99
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#define SISLANDS_DPM2_MAXPS_PERCENT_M 99
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#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
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#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12
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#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
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#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
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#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
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#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10
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#define SISLANDS_VRC_DFLT 0xC000B3
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#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687
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#define SISLANDS_CGULVPARAMETER_DFLT 0x00040035
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#define SISLANDS_CGULVCONTROL_DFLT 0x1f007550
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#endif
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