1173 lines
28 KiB
C
1173 lines
28 KiB
C
/* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
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* irq.c: UltraSparc IRQ handling/init/registry.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/bootmem.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/sbus.h>
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#include <asm/iommu.h>
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#include <asm/upa.h>
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#include <asm/oplib.h>
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#include <asm/timer.h>
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#include <asm/smp.h>
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#include <asm/starfire.h>
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#include <asm/uaccess.h>
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#include <asm/cache.h>
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#include <asm/cpudata.h>
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#include <asm/auxio.h>
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#include <asm/head.h>
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#ifdef CONFIG_SMP
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static void distribute_irqs(void);
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#endif
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/* UPA nodes send interrupt packet to UltraSparc with first data reg
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* value low 5 (7 on Starfire) bits holding the IRQ identifier being
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* delivered. We must translate this into a non-vector IRQ so we can
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* set the softint on this cpu.
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*
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* To make processing these packets efficient and race free we use
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* an array of irq buckets below. The interrupt vector handler in
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* entry.S feeds incoming packets into per-cpu pil-indexed lists.
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* The IVEC handler does not need to act atomically, the PIL dispatch
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* code uses CAS to get an atomic snapshot of the list and clear it
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* at the same time.
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*/
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struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
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/* This has to be in the main kernel image, it cannot be
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* turned into per-cpu data. The reason is that the main
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* kernel image is locked into the TLB and this structure
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* is accessed from the vectored interrupt trap handler. If
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* access to this structure takes a TLB miss it could cause
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* the 5-level sparc v9 trap stack to overflow.
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*/
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struct irq_work_struct {
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unsigned int irq_worklists[16];
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};
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struct irq_work_struct __irq_work[NR_CPUS];
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#define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
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static struct irqaction *irq_action[NR_IRQS+1];
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/* This only synchronizes entities which modify IRQ handler
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* state and some selected user-level spots that want to
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* read things in the table. IRQ handler processing orders
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* its' accesses such that no locking is needed.
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*/
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static DEFINE_SPINLOCK(irq_action_lock);
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static void register_irq_proc (unsigned int irq);
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/*
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* Upper 2b of irqaction->flags holds the ino.
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* irqaction->mask holds the smp affinity information.
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*/
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#define put_ino_in_irqaction(action, irq) \
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action->flags &= 0xffffffffffffUL; \
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if (__bucket(irq) == &pil0_dummy_bucket) \
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action->flags |= 0xdeadUL << 48; \
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else \
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action->flags |= __irq_ino(irq) << 48;
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#define get_ino_in_irqaction(action) (action->flags >> 48)
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#define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
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#define get_smpaff_in_irqaction(action) ((action)->mask)
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int show_interrupts(struct seq_file *p, void *v)
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{
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unsigned long flags;
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int i = *(loff_t *) v;
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struct irqaction *action;
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#ifdef CONFIG_SMP
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int j;
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#endif
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spin_lock_irqsave(&irq_action_lock, flags);
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if (i <= NR_IRQS) {
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if (!(action = *(i + irq_action)))
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goto out_unlock;
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seq_printf(p, "%3d: ", i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j) {
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seq_printf(p, "%10u ",
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kstat_cpu(j).irqs[i]);
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}
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#endif
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seq_printf(p, " %s:%lx", action->name,
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get_ino_in_irqaction(action));
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for (action = action->next; action; action = action->next) {
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seq_printf(p, ", %s:%lx", action->name,
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get_ino_in_irqaction(action));
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}
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seq_putc(p, '\n');
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}
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out_unlock:
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spin_unlock_irqrestore(&irq_action_lock, flags);
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return 0;
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}
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extern unsigned long real_hard_smp_processor_id(void);
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static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
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{
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unsigned int tid;
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if (this_is_starfire) {
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tid = starfire_translate(imap, cpuid);
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tid <<= IMAP_TID_SHIFT;
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tid &= IMAP_TID_UPA;
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} else {
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if (tlb_type == cheetah || tlb_type == cheetah_plus) {
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unsigned long ver;
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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if ((ver >> 32UL) == __JALAPENO_ID ||
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(ver >> 32UL) == __SERRANO_ID) {
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tid = cpuid << IMAP_TID_SHIFT;
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tid &= IMAP_TID_JBUS;
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} else {
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unsigned int a = cpuid & 0x1f;
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unsigned int n = (cpuid >> 5) & 0x1f;
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tid = ((a << IMAP_AID_SHIFT) |
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(n << IMAP_NID_SHIFT));
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tid &= (IMAP_AID_SAFARI |
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IMAP_NID_SAFARI);;
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}
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} else {
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tid = cpuid << IMAP_TID_SHIFT;
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tid &= IMAP_TID_UPA;
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}
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}
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return tid;
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}
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/* Now these are always passed a true fully specified sun4u INO. */
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void enable_irq(unsigned int irq)
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{
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struct ino_bucket *bucket = __bucket(irq);
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unsigned long imap, cpuid;
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imap = bucket->imap;
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if (imap == 0UL)
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return;
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preempt_disable();
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/* This gets the physical processor ID, even on uniprocessor,
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* so we can always program the interrupt target correctly.
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*/
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cpuid = real_hard_smp_processor_id();
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if (tlb_type == hypervisor) {
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unsigned int ino = __irq_ino(irq);
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int err;
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err = sun4v_intr_settarget(ino, cpuid);
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if (err != HV_EOK)
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printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
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ino, cpuid, err);
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err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
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if (err != HV_EOK)
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printk("sun4v_intr_setenabled(%x): err(%d)\n",
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ino, err);
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} else {
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unsigned int tid = sun4u_compute_tid(imap, cpuid);
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/* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
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* of this SYSIO's preconfigured IGN in the SYSIO Control
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* Register, the hardware just mirrors that value here.
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* However for Graphics and UPA Slave devices the full
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* IMAP_INR field can be set by the programmer here.
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*
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* Things like FFB can now be handled via the new IRQ
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* mechanism.
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*/
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upa_writel(tid | IMAP_VALID, imap);
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}
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preempt_enable();
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}
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/* This now gets passed true ino's as well. */
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void disable_irq(unsigned int irq)
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{
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struct ino_bucket *bucket = __bucket(irq);
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unsigned long imap;
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imap = bucket->imap;
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if (imap != 0UL) {
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if (tlb_type == hypervisor) {
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unsigned int ino = __irq_ino(irq);
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int err;
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err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
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if (err != HV_EOK)
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printk("sun4v_intr_setenabled(%x): "
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"err(%d)\n", ino, err);
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} else {
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u32 tmp;
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/* NOTE: We do not want to futz with the IRQ clear registers
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* and move the state to IDLE, the SCSI code does call
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* disable_irq() to assure atomicity in the queue cmd
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* SCSI adapter driver code. Thus we'd lose interrupts.
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*/
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tmp = upa_readl(imap);
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tmp &= ~IMAP_VALID;
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upa_writel(tmp, imap);
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}
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}
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}
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/* The timer is the one "weird" interrupt which is generated by
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* the CPU %tick register and not by some normal vectored interrupt
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* source. To handle this special case, we use this dummy INO bucket.
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*/
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static struct irq_desc pil0_dummy_desc;
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static struct ino_bucket pil0_dummy_bucket = {
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.irq_info = &pil0_dummy_desc,
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};
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static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
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unsigned long iclr, unsigned long imap,
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struct ino_bucket *bucket)
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{
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prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
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"(%d:%d:%016lx:%016lx), halting...\n",
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ino, bucket->pil, bucket->iclr, bucket->imap,
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pil, inofixup, iclr, imap);
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prom_halt();
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}
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unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
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{
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struct ino_bucket *bucket;
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int ino;
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if (pil == 0) {
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if (iclr != 0UL || imap != 0UL) {
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prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
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iclr, imap);
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prom_halt();
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}
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return __irq(&pil0_dummy_bucket);
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}
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BUG_ON(tlb_type == hypervisor);
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/* RULE: Both must be specified in all other cases. */
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if (iclr == 0UL || imap == 0UL) {
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prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
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pil, inofixup, iclr, imap);
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prom_halt();
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}
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ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
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if (ino > NUM_IVECS) {
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prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
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ino, pil, inofixup, iclr, imap);
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prom_halt();
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}
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bucket = &ivector_table[ino];
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if (bucket->flags & IBF_ACTIVE)
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build_irq_error("IRQ: Trying to build active INO bucket.\n",
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ino, pil, inofixup, iclr, imap, bucket);
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if (bucket->irq_info) {
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if (bucket->imap != imap || bucket->iclr != iclr)
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build_irq_error("IRQ: Trying to reinit INO bucket.\n",
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ino, pil, inofixup, iclr, imap, bucket);
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goto out;
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}
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bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
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if (!bucket->irq_info) {
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prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
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prom_halt();
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}
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/* Ok, looks good, set it up. Don't touch the irq_chain or
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* the pending flag.
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*/
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bucket->imap = imap;
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bucket->iclr = iclr;
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bucket->pil = pil;
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bucket->flags = 0;
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out:
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return __irq(bucket);
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}
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unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
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{
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struct ino_bucket *bucket;
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unsigned long sysino;
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sysino = sun4v_devino_to_sysino(devhandle, devino);
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bucket = &ivector_table[sysino];
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/* Catch accidental accesses to these things. IMAP/ICLR handling
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* is done by hypervisor calls on sun4v platforms, not by direct
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* register accesses.
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*
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* But we need to make them look unique for the disable_irq() logic
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* in free_irq().
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*/
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bucket->imap = ~0UL - sysino;
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bucket->iclr = ~0UL - sysino;
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bucket->pil = pil;
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bucket->flags = flags;
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bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC);
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if (!bucket->irq_info) {
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prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
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prom_halt();
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}
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return __irq(bucket);
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}
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static void atomic_bucket_insert(struct ino_bucket *bucket)
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{
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unsigned long pstate;
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unsigned int *ent;
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__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
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__asm__ __volatile__("wrpr %0, %1, %%pstate"
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: : "r" (pstate), "i" (PSTATE_IE));
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ent = irq_work(smp_processor_id(), bucket->pil);
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bucket->irq_chain = *ent;
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*ent = __irq(bucket);
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__asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
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}
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static int check_irq_sharing(int pil, unsigned long irqflags)
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{
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struct irqaction *action, *tmp;
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action = *(irq_action + pil);
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if (action) {
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if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
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for (tmp = action; tmp->next; tmp = tmp->next)
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;
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} else {
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return -EBUSY;
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}
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}
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return 0;
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}
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static void append_irq_action(int pil, struct irqaction *action)
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{
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struct irqaction **pp = irq_action + pil;
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while (*pp)
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pp = &((*pp)->next);
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*pp = action;
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}
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static struct irqaction *get_action_slot(struct ino_bucket *bucket)
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{
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struct irq_desc *desc = bucket->irq_info;
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int max_irq, i;
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max_irq = 1;
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if (bucket->flags & IBF_PCI)
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max_irq = MAX_IRQ_DESC_ACTION;
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for (i = 0; i < max_irq; i++) {
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struct irqaction *p = &desc->action[i];
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u32 mask = (1 << i);
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if (desc->action_active_mask & mask)
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continue;
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desc->action_active_mask |= mask;
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return p;
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}
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return NULL;
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}
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int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
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unsigned long irqflags, const char *name, void *dev_id)
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{
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struct irqaction *action;
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struct ino_bucket *bucket = __bucket(irq);
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unsigned long flags;
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int pending = 0;
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if (unlikely(!handler))
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return -EINVAL;
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if (unlikely(!bucket->irq_info))
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return -ENODEV;
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if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
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/*
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* This function might sleep, we want to call it first,
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* outside of the atomic block. In SA_STATIC_ALLOC case,
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* random driver's kmalloc will fail, but it is safe.
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* If already initialized, random driver will not reinit.
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* Yes, this might clear the entropy pool if the wrong
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* driver is attempted to be loaded, without actually
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* installing a new handler, but is this really a problem,
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* only the sysadmin is able to do this.
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*/
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rand_initialize_irq(irq);
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}
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spin_lock_irqsave(&irq_action_lock, flags);
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if (check_irq_sharing(bucket->pil, irqflags)) {
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spin_unlock_irqrestore(&irq_action_lock, flags);
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return -EBUSY;
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}
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action = get_action_slot(bucket);
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if (!action) {
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spin_unlock_irqrestore(&irq_action_lock, flags);
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return -ENOMEM;
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}
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bucket->flags |= IBF_ACTIVE;
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pending = 0;
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if (bucket != &pil0_dummy_bucket) {
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pending = bucket->pending;
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if (pending)
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bucket->pending = 0;
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}
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action->handler = handler;
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action->flags = irqflags;
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action->name = name;
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action->next = NULL;
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action->dev_id = dev_id;
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put_ino_in_irqaction(action, irq);
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put_smpaff_in_irqaction(action, CPU_MASK_NONE);
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append_irq_action(bucket->pil, action);
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enable_irq(irq);
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/* We ate the IVEC already, this makes sure it does not get lost. */
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if (pending) {
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atomic_bucket_insert(bucket);
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set_softint(1 << bucket->pil);
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}
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spin_unlock_irqrestore(&irq_action_lock, flags);
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if (bucket != &pil0_dummy_bucket)
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register_irq_proc(__irq_ino(irq));
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#ifdef CONFIG_SMP
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distribute_irqs();
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#endif
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return 0;
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}
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EXPORT_SYMBOL(request_irq);
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static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
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{
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struct ino_bucket *bucket = __bucket(irq);
|
|
struct irqaction *action, **pp;
|
|
|
|
pp = irq_action + bucket->pil;
|
|
action = *pp;
|
|
if (unlikely(!action))
|
|
return NULL;
|
|
|
|
if (unlikely(!action->handler)) {
|
|
printk("Freeing free IRQ %d\n", bucket->pil);
|
|
return NULL;
|
|
}
|
|
|
|
while (action && action->dev_id != dev_id) {
|
|
pp = &action->next;
|
|
action = *pp;
|
|
}
|
|
|
|
if (likely(action))
|
|
*pp = action->next;
|
|
|
|
return action;
|
|
}
|
|
|
|
void free_irq(unsigned int irq, void *dev_id)
|
|
{
|
|
struct irqaction *action;
|
|
struct ino_bucket *bucket;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&irq_action_lock, flags);
|
|
|
|
action = unlink_irq_action(irq, dev_id);
|
|
|
|
spin_unlock_irqrestore(&irq_action_lock, flags);
|
|
|
|
if (unlikely(!action))
|
|
return;
|
|
|
|
synchronize_irq(irq);
|
|
|
|
spin_lock_irqsave(&irq_action_lock, flags);
|
|
|
|
bucket = __bucket(irq);
|
|
if (bucket != &pil0_dummy_bucket) {
|
|
struct irq_desc *desc = bucket->irq_info;
|
|
int ent, i;
|
|
|
|
for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
|
|
struct irqaction *p = &desc->action[i];
|
|
|
|
if (p == action) {
|
|
desc->action_active_mask &= ~(1 << i);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!desc->action_active_mask) {
|
|
unsigned long imap = bucket->imap;
|
|
|
|
/* This unique interrupt source is now inactive. */
|
|
bucket->flags &= ~IBF_ACTIVE;
|
|
|
|
/* See if any other buckets share this bucket's IMAP
|
|
* and are still active.
|
|
*/
|
|
for (ent = 0; ent < NUM_IVECS; ent++) {
|
|
struct ino_bucket *bp = &ivector_table[ent];
|
|
if (bp != bucket &&
|
|
bp->imap == imap &&
|
|
(bp->flags & IBF_ACTIVE) != 0)
|
|
break;
|
|
}
|
|
|
|
/* Only disable when no other sub-irq levels of
|
|
* the same IMAP are active.
|
|
*/
|
|
if (ent == NUM_IVECS)
|
|
disable_irq(irq);
|
|
}
|
|
}
|
|
|
|
spin_unlock_irqrestore(&irq_action_lock, flags);
|
|
}
|
|
|
|
EXPORT_SYMBOL(free_irq);
|
|
|
|
#ifdef CONFIG_SMP
|
|
void synchronize_irq(unsigned int irq)
|
|
{
|
|
struct ino_bucket *bucket = __bucket(irq);
|
|
|
|
#if 0
|
|
/* The following is how I wish I could implement this.
|
|
* Unfortunately the ICLR registers are read-only, you can
|
|
* only write ICLR_foo values to them. To get the current
|
|
* IRQ status you would need to get at the IRQ diag registers
|
|
* in the PCI/SBUS controller and the layout of those vary
|
|
* from one controller to the next, sigh... -DaveM
|
|
*/
|
|
unsigned long iclr = bucket->iclr;
|
|
|
|
while (1) {
|
|
u32 tmp = upa_readl(iclr);
|
|
|
|
if (tmp == ICLR_TRANSMIT ||
|
|
tmp == ICLR_PENDING) {
|
|
cpu_relax();
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
#else
|
|
/* So we have to do this with a INPROGRESS bit just like x86. */
|
|
while (bucket->flags & IBF_INPROGRESS)
|
|
cpu_relax();
|
|
#endif
|
|
}
|
|
#endif /* CONFIG_SMP */
|
|
|
|
static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
|
|
{
|
|
struct irq_desc *desc = bp->irq_info;
|
|
unsigned char flags = bp->flags;
|
|
u32 action_mask, i;
|
|
int random;
|
|
|
|
bp->flags |= IBF_INPROGRESS;
|
|
|
|
if (unlikely(!(flags & IBF_ACTIVE))) {
|
|
bp->pending = 1;
|
|
goto out;
|
|
}
|
|
|
|
if (desc->pre_handler)
|
|
desc->pre_handler(bp,
|
|
desc->pre_handler_arg1,
|
|
desc->pre_handler_arg2);
|
|
|
|
action_mask = desc->action_active_mask;
|
|
random = 0;
|
|
for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
|
|
struct irqaction *p = &desc->action[i];
|
|
u32 mask = (1 << i);
|
|
|
|
if (!(action_mask & mask))
|
|
continue;
|
|
|
|
action_mask &= ~mask;
|
|
|
|
if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
|
|
random |= p->flags;
|
|
|
|
if (!action_mask)
|
|
break;
|
|
}
|
|
if (bp->pil != 0) {
|
|
if (tlb_type == hypervisor) {
|
|
unsigned int ino = __irq_ino(bp);
|
|
int err;
|
|
|
|
err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
|
|
if (err != HV_EOK)
|
|
printk("sun4v_intr_setstate(%x): "
|
|
"err(%d)\n", ino, err);
|
|
} else {
|
|
upa_writel(ICLR_IDLE, bp->iclr);
|
|
}
|
|
|
|
/* Test and add entropy */
|
|
if (random & SA_SAMPLE_RANDOM)
|
|
add_interrupt_randomness(irq);
|
|
}
|
|
out:
|
|
bp->flags &= ~IBF_INPROGRESS;
|
|
}
|
|
|
|
void handler_irq(int irq, struct pt_regs *regs)
|
|
{
|
|
struct ino_bucket *bp;
|
|
int cpu = smp_processor_id();
|
|
|
|
#ifndef CONFIG_SMP
|
|
/*
|
|
* Check for TICK_INT on level 14 softint.
|
|
*/
|
|
{
|
|
unsigned long clr_mask = 1 << irq;
|
|
unsigned long tick_mask = tick_ops->softint_mask;
|
|
|
|
if ((irq == 14) && (get_softint() & tick_mask)) {
|
|
irq = 0;
|
|
clr_mask = tick_mask;
|
|
}
|
|
clear_softint(clr_mask);
|
|
}
|
|
#else
|
|
clear_softint(1 << irq);
|
|
#endif
|
|
|
|
irq_enter();
|
|
kstat_this_cpu.irqs[irq]++;
|
|
|
|
/* Sliiiick... */
|
|
#ifndef CONFIG_SMP
|
|
bp = ((irq != 0) ?
|
|
__bucket(xchg32(irq_work(cpu, irq), 0)) :
|
|
&pil0_dummy_bucket);
|
|
#else
|
|
bp = __bucket(xchg32(irq_work(cpu, irq), 0));
|
|
#endif
|
|
while (bp) {
|
|
struct ino_bucket *nbp = __bucket(bp->irq_chain);
|
|
|
|
bp->irq_chain = 0;
|
|
process_bucket(irq, bp, regs);
|
|
bp = nbp;
|
|
}
|
|
irq_exit();
|
|
}
|
|
|
|
#ifdef CONFIG_BLK_DEV_FD
|
|
extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);
|
|
|
|
/* XXX No easy way to include asm/floppy.h XXX */
|
|
extern unsigned char *pdma_vaddr;
|
|
extern unsigned long pdma_size;
|
|
extern volatile int doing_pdma;
|
|
extern unsigned long fdc_status;
|
|
|
|
irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
|
|
{
|
|
if (likely(doing_pdma)) {
|
|
void __iomem *stat = (void __iomem *) fdc_status;
|
|
unsigned char *vaddr = pdma_vaddr;
|
|
unsigned long size = pdma_size;
|
|
u8 val;
|
|
|
|
while (size) {
|
|
val = readb(stat);
|
|
if (unlikely(!(val & 0x80))) {
|
|
pdma_vaddr = vaddr;
|
|
pdma_size = size;
|
|
return IRQ_HANDLED;
|
|
}
|
|
if (unlikely(!(val & 0x20))) {
|
|
pdma_vaddr = vaddr;
|
|
pdma_size = size;
|
|
doing_pdma = 0;
|
|
goto main_interrupt;
|
|
}
|
|
if (val & 0x40) {
|
|
/* read */
|
|
*vaddr++ = readb(stat + 1);
|
|
} else {
|
|
unsigned char data = *vaddr++;
|
|
|
|
/* write */
|
|
writeb(data, stat + 1);
|
|
}
|
|
size--;
|
|
}
|
|
|
|
pdma_vaddr = vaddr;
|
|
pdma_size = size;
|
|
|
|
/* Send Terminal Count pulse to floppy controller. */
|
|
val = readb(auxio_register);
|
|
val |= AUXIO_AUX1_FTCNT;
|
|
writeb(val, auxio_register);
|
|
val &= ~AUXIO_AUX1_FTCNT;
|
|
writeb(val, auxio_register);
|
|
|
|
doing_pdma = 0;
|
|
}
|
|
|
|
main_interrupt:
|
|
return floppy_interrupt(irq, dev_cookie, regs);
|
|
}
|
|
EXPORT_SYMBOL(sparc_floppy_irq);
|
|
#endif
|
|
|
|
/* We really don't need these at all on the Sparc. We only have
|
|
* stubs here because they are exported to modules.
|
|
*/
|
|
unsigned long probe_irq_on(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(probe_irq_on);
|
|
|
|
int probe_irq_off(unsigned long mask)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(probe_irq_off);
|
|
|
|
#ifdef CONFIG_SMP
|
|
static int retarget_one_irq(struct irqaction *p, int goal_cpu)
|
|
{
|
|
struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
|
|
|
|
while (!cpu_online(goal_cpu)) {
|
|
if (++goal_cpu >= NR_CPUS)
|
|
goal_cpu = 0;
|
|
}
|
|
|
|
if (tlb_type == hypervisor) {
|
|
unsigned int ino = __irq_ino(bucket);
|
|
|
|
sun4v_intr_settarget(ino, goal_cpu);
|
|
sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
|
|
} else {
|
|
unsigned long imap = bucket->imap;
|
|
unsigned int tid = sun4u_compute_tid(imap, goal_cpu);
|
|
|
|
upa_writel(tid | IMAP_VALID, imap);
|
|
}
|
|
|
|
do {
|
|
if (++goal_cpu >= NR_CPUS)
|
|
goal_cpu = 0;
|
|
} while (!cpu_online(goal_cpu));
|
|
|
|
return goal_cpu;
|
|
}
|
|
|
|
/* Called from request_irq. */
|
|
static void distribute_irqs(void)
|
|
{
|
|
unsigned long flags;
|
|
int cpu, level;
|
|
|
|
spin_lock_irqsave(&irq_action_lock, flags);
|
|
cpu = 0;
|
|
|
|
/*
|
|
* Skip the timer at [0], and very rare error/power intrs at [15].
|
|
* Also level [12], it causes problems on Ex000 systems.
|
|
*/
|
|
for (level = 1; level < NR_IRQS; level++) {
|
|
struct irqaction *p = irq_action[level];
|
|
|
|
if (level == 12)
|
|
continue;
|
|
|
|
while(p) {
|
|
cpu = retarget_one_irq(p, cpu);
|
|
p = p->next;
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&irq_action_lock, flags);
|
|
}
|
|
#endif
|
|
|
|
struct sun5_timer {
|
|
u64 count0;
|
|
u64 limit0;
|
|
u64 count1;
|
|
u64 limit1;
|
|
};
|
|
|
|
static struct sun5_timer *prom_timers;
|
|
static u64 prom_limit0, prom_limit1;
|
|
|
|
static void map_prom_timers(void)
|
|
{
|
|
unsigned int addr[3];
|
|
int tnode, err;
|
|
|
|
/* PROM timer node hangs out in the top level of device siblings... */
|
|
tnode = prom_finddevice("/counter-timer");
|
|
|
|
/* Assume if node is not present, PROM uses different tick mechanism
|
|
* which we should not care about.
|
|
*/
|
|
if (tnode == 0 || tnode == -1) {
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
return;
|
|
}
|
|
|
|
/* If PROM is really using this, it must be mapped by him. */
|
|
err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
|
|
if (err == -1) {
|
|
prom_printf("PROM does not have timer mapped, trying to continue.\n");
|
|
prom_timers = (struct sun5_timer *) 0;
|
|
return;
|
|
}
|
|
prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
|
|
}
|
|
|
|
static void kill_prom_timer(void)
|
|
{
|
|
if (!prom_timers)
|
|
return;
|
|
|
|
/* Save them away for later. */
|
|
prom_limit0 = prom_timers->limit0;
|
|
prom_limit1 = prom_timers->limit1;
|
|
|
|
/* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
|
|
* We turn both off here just to be paranoid.
|
|
*/
|
|
prom_timers->limit0 = 0;
|
|
prom_timers->limit1 = 0;
|
|
|
|
/* Wheee, eat the interrupt packet too... */
|
|
__asm__ __volatile__(
|
|
" mov 0x40, %%g2\n"
|
|
" ldxa [%%g0] %0, %%g1\n"
|
|
" ldxa [%%g2] %1, %%g1\n"
|
|
" stxa %%g0, [%%g0] %0\n"
|
|
" membar #Sync\n"
|
|
: /* no outputs */
|
|
: "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
|
|
: "g1", "g2");
|
|
}
|
|
|
|
void init_irqwork_curcpu(void)
|
|
{
|
|
int cpu = hard_smp_processor_id();
|
|
|
|
memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
|
|
}
|
|
|
|
static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
|
|
{
|
|
unsigned long num_entries = 128;
|
|
unsigned long status;
|
|
|
|
status = sun4v_cpu_qconf(type, paddr, num_entries);
|
|
if (status != HV_EOK) {
|
|
prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
|
|
"err %lu\n", type, paddr, num_entries, status);
|
|
prom_halt();
|
|
}
|
|
}
|
|
|
|
static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
|
|
{
|
|
struct trap_per_cpu *tb = &trap_block[this_cpu];
|
|
|
|
register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
|
|
register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
|
|
register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
|
|
register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
|
|
}
|
|
|
|
static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
|
|
{
|
|
void *page;
|
|
|
|
if (use_bootmem)
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
else
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page) {
|
|
prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
*pa_ptr = __pa(page);
|
|
}
|
|
|
|
static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
|
|
{
|
|
void *page;
|
|
|
|
if (use_bootmem)
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
else
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page) {
|
|
prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
*pa_ptr = __pa(page);
|
|
}
|
|
|
|
static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
void *page;
|
|
|
|
BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
|
|
|
|
if (use_bootmem)
|
|
page = alloc_bootmem_low_pages(PAGE_SIZE);
|
|
else
|
|
page = (void *) get_zeroed_page(GFP_ATOMIC);
|
|
|
|
if (!page) {
|
|
prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
tb->cpu_mondo_block_pa = __pa(page);
|
|
tb->cpu_list_pa = __pa(page + 64);
|
|
#endif
|
|
}
|
|
|
|
/* Allocate and register the mondo and error queues for this cpu. */
|
|
void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load)
|
|
{
|
|
struct trap_per_cpu *tb = &trap_block[cpu];
|
|
|
|
if (alloc) {
|
|
alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
|
|
alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
|
|
alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
|
|
alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
|
|
alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
|
|
alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
|
|
|
|
init_cpu_send_mondo_info(tb, use_bootmem);
|
|
}
|
|
|
|
if (load) {
|
|
if (cpu != hard_smp_processor_id()) {
|
|
prom_printf("SUN4V: init mondo on cpu %d not %d\n",
|
|
cpu, hard_smp_processor_id());
|
|
prom_halt();
|
|
}
|
|
sun4v_register_mondo_queues(cpu);
|
|
}
|
|
}
|
|
|
|
/* Only invoked on boot processor. */
|
|
void __init init_IRQ(void)
|
|
{
|
|
map_prom_timers();
|
|
kill_prom_timer();
|
|
memset(&ivector_table[0], 0, sizeof(ivector_table));
|
|
|
|
if (tlb_type == hypervisor)
|
|
sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
|
|
|
|
/* We need to clear any IRQ's pending in the soft interrupt
|
|
* registers, a spurious one could be left around from the
|
|
* PROM timer which we just disabled.
|
|
*/
|
|
clear_softint(get_softint());
|
|
|
|
/* Now that ivector table is initialized, it is safe
|
|
* to receive IRQ vector traps. We will normally take
|
|
* one or two right now, in case some device PROM used
|
|
* to boot us wants to speak to us. We just ignore them.
|
|
*/
|
|
__asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
|
|
"or %%g1, %0, %%g1\n\t"
|
|
"wrpr %%g1, 0x0, %%pstate"
|
|
: /* No outputs */
|
|
: "i" (PSTATE_IE)
|
|
: "g1");
|
|
}
|
|
|
|
static struct proc_dir_entry * root_irq_dir;
|
|
static struct proc_dir_entry * irq_dir [NUM_IVECS];
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static int irq_affinity_read_proc (char *page, char **start, off_t off,
|
|
int count, int *eof, void *data)
|
|
{
|
|
struct ino_bucket *bp = ivector_table + (long)data;
|
|
struct irq_desc *desc = bp->irq_info;
|
|
struct irqaction *ap = desc->action;
|
|
cpumask_t mask;
|
|
int len;
|
|
|
|
mask = get_smpaff_in_irqaction(ap);
|
|
if (cpus_empty(mask))
|
|
mask = cpu_online_map;
|
|
|
|
len = cpumask_scnprintf(page, count, mask);
|
|
if (count - len < 2)
|
|
return -EINVAL;
|
|
len += sprintf(page + len, "\n");
|
|
return len;
|
|
}
|
|
|
|
static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
|
|
{
|
|
struct ino_bucket *bp = ivector_table + irq;
|
|
struct irq_desc *desc = bp->irq_info;
|
|
struct irqaction *ap = desc->action;
|
|
|
|
/* Users specify affinity in terms of hw cpu ids.
|
|
* As soon as we do this, handler_irq() might see and take action.
|
|
*/
|
|
put_smpaff_in_irqaction(ap, hw_aff);
|
|
|
|
/* Migration is simply done by the next cpu to service this
|
|
* interrupt.
|
|
*/
|
|
}
|
|
|
|
static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
|
|
unsigned long count, void *data)
|
|
{
|
|
int irq = (long) data, full_count = count, err;
|
|
cpumask_t new_value;
|
|
|
|
err = cpumask_parse(buffer, count, new_value);
|
|
|
|
/*
|
|
* Do not allow disabling IRQs completely - it's a too easy
|
|
* way to make the system unusable accidentally :-) At least
|
|
* one online CPU still has to be targeted.
|
|
*/
|
|
cpus_and(new_value, new_value, cpu_online_map);
|
|
if (cpus_empty(new_value))
|
|
return -EINVAL;
|
|
|
|
set_intr_affinity(irq, new_value);
|
|
|
|
return full_count;
|
|
}
|
|
|
|
#endif
|
|
|
|
#define MAX_NAMELEN 10
|
|
|
|
static void register_irq_proc (unsigned int irq)
|
|
{
|
|
char name [MAX_NAMELEN];
|
|
|
|
if (!root_irq_dir || irq_dir[irq])
|
|
return;
|
|
|
|
memset(name, 0, MAX_NAMELEN);
|
|
sprintf(name, "%x", irq);
|
|
|
|
/* create /proc/irq/1234 */
|
|
irq_dir[irq] = proc_mkdir(name, root_irq_dir);
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* XXX SMP affinity not supported on starfire yet. */
|
|
if (this_is_starfire == 0) {
|
|
struct proc_dir_entry *entry;
|
|
|
|
/* create /proc/irq/1234/smp_affinity */
|
|
entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
|
|
|
|
if (entry) {
|
|
entry->nlink = 1;
|
|
entry->data = (void *)(long)irq;
|
|
entry->read_proc = irq_affinity_read_proc;
|
|
entry->write_proc = irq_affinity_write_proc;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void init_irq_proc (void)
|
|
{
|
|
/* create /proc/irq */
|
|
root_irq_dir = proc_mkdir("irq", NULL);
|
|
}
|
|
|