430 lines
12 KiB
C
430 lines
12 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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#include <drm/drmP.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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/* rs400,rs480 depends on : */
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void r100_hdp_reset(struct radeon_device *rdev);
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void r100_mc_disable_clients(struct radeon_device *rdev);
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int r300_mc_wait_for_idle(struct radeon_device *rdev);
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void r420_pipes_init(struct radeon_device *rdev);
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/* This files gather functions specifics to :
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* rs400,rs480
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*
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* Some of these functions might be used by newer ASICs.
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*/
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void rs400_gpu_init(struct radeon_device *rdev);
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int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
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/*
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* GART functions.
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*/
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void rs400_gart_adjust_size(struct radeon_device *rdev)
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{
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/* Check gart size */
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switch (rdev->mc.gtt_size/(1024*1024)) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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case 1024:
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case 2048:
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break;
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default:
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DRM_ERROR("Unable to use IGP GART size %uM\n",
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(unsigned)(rdev->mc.gtt_size >> 20));
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DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
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DRM_ERROR("Forcing to 32M GART size\n");
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rdev->mc.gtt_size = 32 * 1024 * 1024;
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return;
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}
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
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/* FIXME: RS400 & RS480 seems to have issue with GART size
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* if 4G of system memory (needs more testing) */
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rdev->mc.gtt_size = 32 * 1024 * 1024;
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DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
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}
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}
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void rs400_gart_tlb_flush(struct radeon_device *rdev)
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{
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uint32_t tmp;
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unsigned int timeout = rdev->usec_timeout;
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WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
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do {
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tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
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if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
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break;
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DRM_UDELAY(1);
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timeout--;
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} while (timeout > 0);
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WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
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}
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int rs400_gart_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->gart.table.ram.ptr) {
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WARN(1, "RS400 GART already initialized.\n");
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return 0;
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}
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/* Check gart size */
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switch(rdev->mc.gtt_size / (1024 * 1024)) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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case 1024:
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case 2048:
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break;
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default:
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return -EINVAL;
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}
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/* Initialize common gart structure */
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r = radeon_gart_init(rdev);
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if (r)
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return r;
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if (rs400_debugfs_pcie_gart_info_init(rdev))
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DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
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rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
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return radeon_gart_table_ram_alloc(rdev);
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}
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int rs400_gart_enable(struct radeon_device *rdev)
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{
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uint32_t size_reg;
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uint32_t tmp;
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
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/* Check gart size */
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switch(rdev->mc.gtt_size / (1024 * 1024)) {
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case 32:
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size_reg = RS480_VA_SIZE_32MB;
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break;
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case 64:
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size_reg = RS480_VA_SIZE_64MB;
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break;
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case 128:
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size_reg = RS480_VA_SIZE_128MB;
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break;
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case 256:
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size_reg = RS480_VA_SIZE_256MB;
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break;
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case 512:
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size_reg = RS480_VA_SIZE_512MB;
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break;
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case 1024:
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size_reg = RS480_VA_SIZE_1GB;
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break;
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case 2048:
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size_reg = RS480_VA_SIZE_2GB;
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break;
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default:
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return -EINVAL;
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}
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/* It should be fine to program it to max value */
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if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
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WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
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WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
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} else {
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WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
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WREG32(RS480_AGP_BASE_2, 0);
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}
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tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
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tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
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tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
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if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
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WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
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tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
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WREG32(RADEON_BUS_CNTL, tmp);
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} else {
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WREG32(RADEON_MC_AGP_LOCATION, tmp);
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tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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WREG32(RADEON_BUS_CNTL, tmp);
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}
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/* Table should be in 32bits address space so ignore bits above. */
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tmp = (u32)rdev->gart.table_addr & 0xfffff000;
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tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
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WREG32_MC(RS480_GART_BASE, tmp);
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/* TODO: more tweaking here */
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WREG32_MC(RS480_GART_FEATURE_ID,
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(RS480_TLB_ENABLE |
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RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
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/* Disable snooping */
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WREG32_MC(RS480_AGP_MODE_CNTL,
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(1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
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/* Disable AGP mode */
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/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
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* AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
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if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
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WREG32_MC(RS480_MC_MISC_CNTL,
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(RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
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} else {
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WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
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}
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/* Enable gart */
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WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
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rs400_gart_tlb_flush(rdev);
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rdev->gart.ready = true;
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return 0;
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}
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void rs400_gart_disable(struct radeon_device *rdev)
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{
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uint32_t tmp;
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
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WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
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}
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void rs400_gart_fini(struct radeon_device *rdev)
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{
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rs400_gart_disable(rdev);
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radeon_gart_table_ram_free(rdev);
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radeon_gart_fini(rdev);
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}
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int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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{
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uint32_t entry;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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entry = (lower_32_bits(addr) & PAGE_MASK) |
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((upper_32_bits(addr) & 0xff) << 4) |
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0xc;
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entry = cpu_to_le32(entry);
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rdev->gart.table.ram.ptr[i] = entry;
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return 0;
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}
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/*
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* MC functions.
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*/
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int rs400_mc_init(struct radeon_device *rdev)
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{
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uint32_t tmp;
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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rs400_gpu_init(rdev);
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rs400_gart_disable(rdev);
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rdev->mc.gtt_location = rdev->mc.mc_vram_size;
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rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
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rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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r100_mc_disable_clients(rdev);
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if (r300_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
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tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
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tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
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WREG32(RADEON_MC_FB_LOCATION, tmp);
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tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS;
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WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
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(void)RREG32(RADEON_HOST_PATH_CNTL);
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WREG32(RADEON_HOST_PATH_CNTL, tmp);
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(void)RREG32(RADEON_HOST_PATH_CNTL);
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return 0;
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}
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void rs400_mc_fini(struct radeon_device *rdev)
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{
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}
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/*
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* Global GPU functions
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*/
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void rs400_errata(struct radeon_device *rdev)
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{
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rdev->pll_errata = 0;
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}
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void rs400_gpu_init(struct radeon_device *rdev)
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{
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/* FIXME: HDP same place on rs400 ? */
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r100_hdp_reset(rdev);
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/* FIXME: is this correct ? */
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r420_pipes_init(rdev);
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if (r300_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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/*
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* VRAM info.
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*/
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void rs400_vram_info(struct radeon_device *rdev)
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{
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rs400_gart_adjust_size(rdev);
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/* DDR for all card after R300 & IGP */
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rdev->mc.vram_is_ddr = true;
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rdev->mc.vram_width = 128;
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r100_vram_init_sizes(rdev);
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}
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/*
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* Indirect registers accessor
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*/
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uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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uint32_t r;
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WREG32(RS480_NB_MC_INDEX, reg & 0xff);
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r = RREG32(RS480_NB_MC_DATA);
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WREG32(RS480_NB_MC_INDEX, 0xff);
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return r;
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}
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void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
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WREG32(RS480_NB_MC_DATA, (v));
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WREG32(RS480_NB_MC_INDEX, 0xff);
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t tmp;
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tmp = RREG32(RADEON_HOST_PATH_CNTL);
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seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
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tmp = RREG32(RADEON_BUS_CNTL);
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seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
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if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
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tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
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seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
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seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
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seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
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tmp = RREG32_MC(0x100);
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seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
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tmp = RREG32(0x134);
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seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
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} else {
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tmp = RREG32(RADEON_AGP_BASE);
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seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
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tmp = RREG32(RS480_AGP_BASE_2);
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seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
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tmp = RREG32(RADEON_MC_AGP_LOCATION);
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seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
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}
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tmp = RREG32_MC(RS480_GART_BASE);
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seq_printf(m, "GART_BASE 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_GART_FEATURE_ID);
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seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
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seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_MC_MISC_CNTL);
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seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
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tmp = RREG32_MC(0x5F);
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seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
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seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
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seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
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tmp = RREG32_MC(0x3B);
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seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
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tmp = RREG32_MC(0x3C);
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seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
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tmp = RREG32_MC(0x30);
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seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
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tmp = RREG32_MC(0x31);
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seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
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tmp = RREG32_MC(0x32);
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seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
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tmp = RREG32_MC(0x33);
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seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
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tmp = RREG32_MC(0x34);
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seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
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tmp = RREG32_MC(0x35);
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seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
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tmp = RREG32_MC(0x36);
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seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
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tmp = RREG32_MC(0x37);
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seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
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return 0;
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}
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static struct drm_info_list rs400_gart_info_list[] = {
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{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
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};
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#endif
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int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
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#else
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return 0;
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#endif
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}
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