827 lines
17 KiB
C
827 lines
17 KiB
C
/*
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* MPC85xx Device descriptions
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*
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/serial_8250.h>
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#include <linux/fsl_devices.h>
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#include <linux/fs_enet_pd.h>
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#include <asm/mpc85xx.h>
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#include <asm/irq.h>
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#include <asm/ppc_sys.h>
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#include <asm/cpm2.h>
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/* We use offsets for IORESOURCE_MEM since we do not know at compile time
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* what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
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*/
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struct gianfar_mdio_data mpc85xx_mdio_pdata = {
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};
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static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
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.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
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FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
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FSL_GIANFAR_DEV_HAS_MULTI_INTR,
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};
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static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
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.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
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FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
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FSL_GIANFAR_DEV_HAS_MULTI_INTR,
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};
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static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
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.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
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FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
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FSL_GIANFAR_DEV_HAS_MULTI_INTR |
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FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
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FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
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};
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static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
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.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
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FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
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FSL_GIANFAR_DEV_HAS_MULTI_INTR |
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FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
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FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
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};
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static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
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.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
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FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
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FSL_GIANFAR_DEV_HAS_MULTI_INTR |
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FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
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FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
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};
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static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
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.device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
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FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
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FSL_GIANFAR_DEV_HAS_MULTI_INTR |
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FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
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FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
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};
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static struct gianfar_platform_data mpc85xx_fec_pdata = {
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.device_flags = 0,
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};
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static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
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.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
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};
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static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
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.device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
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};
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static struct fs_platform_info mpc85xx_fcc1_pdata = {
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.fs_no = fsid_fcc1,
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.cp_page = CPM_CR_FCC1_PAGE,
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.cp_block = CPM_CR_FCC1_SBLOCK,
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.rx_ring = 32,
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.tx_ring = 32,
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.rx_copybreak = 240,
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.use_napi = 0,
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.napi_weight = 17,
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.clk_mask = CMX1_CLK_MASK,
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.clk_route = CMX1_CLK_ROUTE,
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.clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
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.mem_offset = FCC1_MEM_OFFSET,
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};
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static struct fs_platform_info mpc85xx_fcc2_pdata = {
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.fs_no = fsid_fcc2,
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.cp_page = CPM_CR_FCC2_PAGE,
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.cp_block = CPM_CR_FCC2_SBLOCK,
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.rx_ring = 32,
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.tx_ring = 32,
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.rx_copybreak = 240,
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.use_napi = 0,
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.napi_weight = 17,
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.clk_mask = CMX2_CLK_MASK,
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.clk_route = CMX2_CLK_ROUTE,
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.clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
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.mem_offset = FCC2_MEM_OFFSET,
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};
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static struct fs_platform_info mpc85xx_fcc3_pdata = {
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.fs_no = fsid_fcc3,
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.cp_page = CPM_CR_FCC3_PAGE,
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.cp_block = CPM_CR_FCC3_SBLOCK,
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.rx_ring = 32,
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.tx_ring = 32,
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.rx_copybreak = 240,
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.use_napi = 0,
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.napi_weight = 17,
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.clk_mask = CMX3_CLK_MASK,
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.clk_route = CMX3_CLK_ROUTE,
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.clk_trx = (PC_F3RXCLK | PC_F3TXCLK),
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.mem_offset = FCC3_MEM_OFFSET,
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};
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static struct plat_serial8250_port serial_platform_data[] = {
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[0] = {
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.mapbase = 0x4500,
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.irq = MPC85xx_IRQ_DUART,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
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},
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[1] = {
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.mapbase = 0x4600,
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.irq = MPC85xx_IRQ_DUART,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
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},
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{ },
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};
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struct platform_device ppc_sys_platform_devices[] = {
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[MPC85xx_TSEC1] = {
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.name = "fsl-gianfar",
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.id = 1,
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.dev.platform_data = &mpc85xx_tsec1_pdata,
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.num_resources = 4,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_ENET1_OFFSET,
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.end = MPC85xx_ENET1_OFFSET +
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MPC85xx_ENET1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "tx",
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.start = MPC85xx_IRQ_TSEC1_TX,
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.end = MPC85xx_IRQ_TSEC1_TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = MPC85xx_IRQ_TSEC1_RX,
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.end = MPC85xx_IRQ_TSEC1_RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "error",
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.start = MPC85xx_IRQ_TSEC1_ERROR,
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.end = MPC85xx_IRQ_TSEC1_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_TSEC2] = {
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.name = "fsl-gianfar",
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.id = 2,
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.dev.platform_data = &mpc85xx_tsec2_pdata,
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.num_resources = 4,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_ENET2_OFFSET,
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.end = MPC85xx_ENET2_OFFSET +
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MPC85xx_ENET2_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "tx",
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.start = MPC85xx_IRQ_TSEC2_TX,
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.end = MPC85xx_IRQ_TSEC2_TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = MPC85xx_IRQ_TSEC2_RX,
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.end = MPC85xx_IRQ_TSEC2_RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "error",
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.start = MPC85xx_IRQ_TSEC2_ERROR,
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.end = MPC85xx_IRQ_TSEC2_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_FEC] = {
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.name = "fsl-gianfar",
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.id = 3,
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.dev.platform_data = &mpc85xx_fec_pdata,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_ENET3_OFFSET,
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.end = MPC85xx_ENET3_OFFSET +
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MPC85xx_ENET3_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_FEC,
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.end = MPC85xx_IRQ_FEC,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_IIC1] = {
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.name = "fsl-i2c",
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.id = 1,
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.dev.platform_data = &mpc85xx_fsl_i2c_pdata,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_IIC1_OFFSET,
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.end = MPC85xx_IIC1_OFFSET +
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MPC85xx_IIC1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_IIC1,
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.end = MPC85xx_IRQ_IIC1,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_DMA0] = {
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.name = "fsl-dma",
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.id = 0,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_DMA0_OFFSET,
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.end = MPC85xx_DMA0_OFFSET +
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MPC85xx_DMA0_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_DMA0,
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.end = MPC85xx_IRQ_DMA0,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_DMA1] = {
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.name = "fsl-dma",
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.id = 1,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_DMA1_OFFSET,
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.end = MPC85xx_DMA1_OFFSET +
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MPC85xx_DMA1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_DMA1,
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.end = MPC85xx_IRQ_DMA1,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_DMA2] = {
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.name = "fsl-dma",
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.id = 2,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_DMA2_OFFSET,
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.end = MPC85xx_DMA2_OFFSET +
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MPC85xx_DMA2_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_DMA2,
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.end = MPC85xx_IRQ_DMA2,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_DMA3] = {
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.name = "fsl-dma",
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.id = 3,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_DMA3_OFFSET,
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.end = MPC85xx_DMA3_OFFSET +
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MPC85xx_DMA3_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_DMA3,
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.end = MPC85xx_IRQ_DMA3,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_DUART] = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev.platform_data = serial_platform_data,
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},
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[MPC85xx_PERFMON] = {
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.name = "fsl-perfmon",
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.id = 1,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_PERFMON_OFFSET,
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.end = MPC85xx_PERFMON_OFFSET +
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MPC85xx_PERFMON_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_PERFMON,
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.end = MPC85xx_IRQ_PERFMON,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_SEC2] = {
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.name = "fsl-sec2",
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.id = 1,
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.num_resources = 2,
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.resource = (struct resource[]) {
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{
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.start = MPC85xx_SEC2_OFFSET,
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.end = MPC85xx_SEC2_OFFSET +
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MPC85xx_SEC2_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MPC85xx_IRQ_SEC2,
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.end = MPC85xx_IRQ_SEC2,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_CPM_FCC1] = {
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.name = "fsl-cpm-fcc",
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.id = 1,
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.num_resources = 4,
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.dev.platform_data = &mpc85xx_fcc1_pdata,
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.resource = (struct resource[]) {
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{
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.name = "fcc_regs",
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.start = 0x91300,
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.end = 0x9131F,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "fcc_regs_c",
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.start = 0x91380,
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.end = 0x9139F,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "fcc_pram",
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.start = 0x88400,
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.end = 0x884ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = SIU_INT_FCC1,
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.end = SIU_INT_FCC1,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_CPM_FCC2] = {
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.name = "fsl-cpm-fcc",
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.id = 2,
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.num_resources = 4,
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.dev.platform_data = &mpc85xx_fcc2_pdata,
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.resource = (struct resource[]) {
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{
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.name = "fcc_regs",
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.start = 0x91320,
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.end = 0x9133F,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "fcc_regs_c",
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.start = 0x913A0,
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.end = 0x913CF,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "fcc_pram",
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.start = 0x88500,
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.end = 0x885ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = SIU_INT_FCC2,
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.end = SIU_INT_FCC2,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_CPM_FCC3] = {
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.name = "fsl-cpm-fcc",
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.id = 3,
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.num_resources = 4,
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.dev.platform_data = &mpc85xx_fcc3_pdata,
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.resource = (struct resource[]) {
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{
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.name = "fcc_regs",
|
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.start = 0x91340,
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.end = 0x9135F,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "fcc_regs_c",
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.start = 0x913D0,
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.end = 0x913FF,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "fcc_pram",
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.start = 0x88600,
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.end = 0x886ff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = SIU_INT_FCC3,
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.end = SIU_INT_FCC3,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
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[MPC85xx_CPM_I2C] = {
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.name = "fsl-cpm-i2c",
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.id = 1,
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.num_resources = 2,
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.resource = (struct resource[]) {
|
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{
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.start = 0x91860,
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.end = 0x918BF,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = SIU_INT_I2C,
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.end = SIU_INT_I2C,
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.flags = IORESOURCE_IRQ,
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},
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},
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},
|
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[MPC85xx_CPM_SCC1] = {
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.name = "fsl-cpm-scc",
|
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.id = 1,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91A00,
|
|
.end = 0x91A1F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_SCC1,
|
|
.end = SIU_INT_SCC1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_SCC2] = {
|
|
.name = "fsl-cpm-scc",
|
|
.id = 2,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91A20,
|
|
.end = 0x91A3F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_SCC2,
|
|
.end = SIU_INT_SCC2,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_SCC3] = {
|
|
.name = "fsl-cpm-scc",
|
|
.id = 3,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91A40,
|
|
.end = 0x91A5F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_SCC3,
|
|
.end = SIU_INT_SCC3,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_SCC4] = {
|
|
.name = "fsl-cpm-scc",
|
|
.id = 4,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91A60,
|
|
.end = 0x91A7F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_SCC4,
|
|
.end = SIU_INT_SCC4,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_SPI] = {
|
|
.name = "fsl-cpm-spi",
|
|
.id = 1,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91AA0,
|
|
.end = 0x91AFF,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_SPI,
|
|
.end = SIU_INT_SPI,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_MCC1] = {
|
|
.name = "fsl-cpm-mcc",
|
|
.id = 1,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91B30,
|
|
.end = 0x91B3F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_MCC1,
|
|
.end = SIU_INT_MCC1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_MCC2] = {
|
|
.name = "fsl-cpm-mcc",
|
|
.id = 2,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91B50,
|
|
.end = 0x91B5F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_MCC2,
|
|
.end = SIU_INT_MCC2,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_SMC1] = {
|
|
.name = "fsl-cpm-smc",
|
|
.id = 1,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91A80,
|
|
.end = 0x91A8F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_SMC1,
|
|
.end = SIU_INT_SMC1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_SMC2] = {
|
|
.name = "fsl-cpm-smc",
|
|
.id = 2,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91A90,
|
|
.end = 0x91A9F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_SMC2,
|
|
.end = SIU_INT_SMC2,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_CPM_USB] = {
|
|
.name = "fsl-cpm-usb",
|
|
.id = 2,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x91B60,
|
|
.end = 0x91B7F,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = SIU_INT_USB,
|
|
.end = SIU_INT_USB,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_eTSEC1] = {
|
|
.name = "fsl-gianfar",
|
|
.id = 1,
|
|
.dev.platform_data = &mpc85xx_etsec1_pdata,
|
|
.num_resources = 4,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = MPC85xx_ENET1_OFFSET,
|
|
.end = MPC85xx_ENET1_OFFSET +
|
|
MPC85xx_ENET1_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "tx",
|
|
.start = MPC85xx_IRQ_TSEC1_TX,
|
|
.end = MPC85xx_IRQ_TSEC1_TX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "rx",
|
|
.start = MPC85xx_IRQ_TSEC1_RX,
|
|
.end = MPC85xx_IRQ_TSEC1_RX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "error",
|
|
.start = MPC85xx_IRQ_TSEC1_ERROR,
|
|
.end = MPC85xx_IRQ_TSEC1_ERROR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_eTSEC2] = {
|
|
.name = "fsl-gianfar",
|
|
.id = 2,
|
|
.dev.platform_data = &mpc85xx_etsec2_pdata,
|
|
.num_resources = 4,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = MPC85xx_ENET2_OFFSET,
|
|
.end = MPC85xx_ENET2_OFFSET +
|
|
MPC85xx_ENET2_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "tx",
|
|
.start = MPC85xx_IRQ_TSEC2_TX,
|
|
.end = MPC85xx_IRQ_TSEC2_TX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "rx",
|
|
.start = MPC85xx_IRQ_TSEC2_RX,
|
|
.end = MPC85xx_IRQ_TSEC2_RX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "error",
|
|
.start = MPC85xx_IRQ_TSEC2_ERROR,
|
|
.end = MPC85xx_IRQ_TSEC2_ERROR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_eTSEC3] = {
|
|
.name = "fsl-gianfar",
|
|
.id = 3,
|
|
.dev.platform_data = &mpc85xx_etsec3_pdata,
|
|
.num_resources = 4,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = MPC85xx_ENET3_OFFSET,
|
|
.end = MPC85xx_ENET3_OFFSET +
|
|
MPC85xx_ENET3_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "tx",
|
|
.start = MPC85xx_IRQ_TSEC3_TX,
|
|
.end = MPC85xx_IRQ_TSEC3_TX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "rx",
|
|
.start = MPC85xx_IRQ_TSEC3_RX,
|
|
.end = MPC85xx_IRQ_TSEC3_RX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "error",
|
|
.start = MPC85xx_IRQ_TSEC3_ERROR,
|
|
.end = MPC85xx_IRQ_TSEC3_ERROR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_eTSEC4] = {
|
|
.name = "fsl-gianfar",
|
|
.id = 4,
|
|
.dev.platform_data = &mpc85xx_etsec4_pdata,
|
|
.num_resources = 4,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x27000,
|
|
.end = 0x27fff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.name = "tx",
|
|
.start = MPC85xx_IRQ_TSEC4_TX,
|
|
.end = MPC85xx_IRQ_TSEC4_TX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "rx",
|
|
.start = MPC85xx_IRQ_TSEC4_RX,
|
|
.end = MPC85xx_IRQ_TSEC4_RX,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.name = "error",
|
|
.start = MPC85xx_IRQ_TSEC4_ERROR,
|
|
.end = MPC85xx_IRQ_TSEC4_ERROR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_IIC2] = {
|
|
.name = "fsl-i2c",
|
|
.id = 2,
|
|
.dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
|
|
.num_resources = 2,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x03100,
|
|
.end = 0x031ff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
.start = MPC85xx_IRQ_IIC1,
|
|
.end = MPC85xx_IRQ_IIC1,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
},
|
|
},
|
|
[MPC85xx_MDIO] = {
|
|
.name = "fsl-gianfar_mdio",
|
|
.id = 0,
|
|
.dev.platform_data = &mpc85xx_mdio_pdata,
|
|
.num_resources = 1,
|
|
.resource = (struct resource[]) {
|
|
{
|
|
.start = 0x24520,
|
|
.end = 0x2453f,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
},
|
|
},
|
|
};
|
|
|
|
static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
|
|
{
|
|
ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
|
|
return 0;
|
|
}
|
|
|
|
static int __init mach_mpc85xx_init(void)
|
|
{
|
|
ppc_sys_device_fixup = mach_mpc85xx_fixup;
|
|
return 0;
|
|
}
|
|
|
|
postcore_initcall(mach_mpc85xx_init);
|