768 lines
18 KiB
C
768 lines
18 KiB
C
/*
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* TI DaVinci DM644x chip specific setup
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*
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* Author: Kevin Hilman, Deep Root Systems, LLC
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*
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* 2007 (c) Deep Root Systems, LLC. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip/irq-davinci-aintc.h>
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#include <linux/platform_data/edma.h>
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#include <linux/platform_data/gpio-davinci.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <mach/cputype.h>
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#include <mach/mux.h>
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#include <mach/serial.h>
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#include <clocksource/timer-davinci.h>
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#include "asp.h"
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#include "davinci.h"
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#include "irqs.h"
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#include "mux.h"
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/*
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* Device specific clocks
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*/
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#define DM644X_REF_FREQ 27000000
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#define DM644X_EMAC_BASE 0x01c80000
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#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
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#define DM644X_EMAC_CNTRL_OFFSET 0x0000
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#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
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#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
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#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
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static struct emac_platform_data dm644x_emac_pdata = {
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.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
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.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
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.ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
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.ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
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.version = EMAC_VERSION_1,
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};
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static struct resource dm644x_emac_resources[] = {
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{
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.start = DM644X_EMAC_BASE,
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.end = DM644X_EMAC_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
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.end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dm644x_emac_device = {
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.name = "davinci_emac",
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.id = 1,
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.dev = {
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.platform_data = &dm644x_emac_pdata,
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},
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.num_resources = ARRAY_SIZE(dm644x_emac_resources),
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.resource = dm644x_emac_resources,
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};
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static struct resource dm644x_mdio_resources[] = {
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{
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.start = DM644X_EMAC_MDIO_BASE,
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.end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm644x_mdio_device = {
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.name = "davinci_mdio",
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.id = 0,
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.num_resources = ARRAY_SIZE(dm644x_mdio_resources),
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.resource = dm644x_mdio_resources,
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};
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/*
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* Device specific mux setup
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*
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* soc description mux mode mode mux dbg
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* reg offset mask mode
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*/
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static const struct mux_config dm644x_pins[] = {
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#ifdef CONFIG_DAVINCI_MUX
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MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
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MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
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MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
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MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
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MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
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MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
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MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
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MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
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MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
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MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
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MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
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MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
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MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
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MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
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MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
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MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
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MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
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MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
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MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
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MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
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MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
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MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
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MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
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MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
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MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
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MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
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MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
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MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
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MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
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MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
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#endif
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};
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/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
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static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_VDINT0] = 2,
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[IRQ_VDINT1] = 6,
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[IRQ_VDINT2] = 6,
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[IRQ_HISTINT] = 6,
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[IRQ_H3AINT] = 6,
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[IRQ_PRVUINT] = 6,
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[IRQ_RSZINT] = 6,
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[7] = 7,
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[IRQ_VENCINT] = 6,
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[IRQ_ASQINT] = 6,
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[IRQ_IMXINT] = 6,
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[IRQ_VLCDINT] = 6,
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[IRQ_USBINT] = 4,
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[IRQ_EMACINT] = 4,
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[14] = 7,
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[15] = 7,
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[IRQ_CCINT0] = 5, /* dma */
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[IRQ_CCERRINT] = 5, /* dma */
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[IRQ_TCERRINT0] = 5, /* dma */
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[IRQ_TCERRINT] = 5, /* dma */
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[IRQ_PSCIN] = 7,
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[21] = 7,
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[IRQ_IDE] = 4,
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[23] = 7,
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[IRQ_MBXINT] = 7,
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[IRQ_MBRINT] = 7,
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[IRQ_MMCINT] = 7,
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[IRQ_SDIOINT] = 7,
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[28] = 7,
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[IRQ_DDRINT] = 7,
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[IRQ_AEMIFINT] = 7,
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[IRQ_VLQINT] = 4,
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[IRQ_TINT0_TINT12] = 2, /* clockevent */
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[IRQ_TINT0_TINT34] = 2, /* clocksource */
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[IRQ_TINT1_TINT12] = 7, /* DSP timer */
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[IRQ_TINT1_TINT34] = 7, /* system tick */
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[IRQ_PWMINT0] = 7,
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[IRQ_PWMINT1] = 7,
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[IRQ_PWMINT2] = 7,
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[IRQ_I2C] = 3,
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[IRQ_UARTINT0] = 3,
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[IRQ_UARTINT1] = 3,
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[IRQ_UARTINT2] = 3,
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[IRQ_SPINT0] = 3,
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[IRQ_SPINT1] = 3,
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[45] = 7,
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[IRQ_DSP2ARM0] = 4,
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[IRQ_DSP2ARM1] = 4,
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[IRQ_GPIO0] = 7,
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[IRQ_GPIO1] = 7,
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[IRQ_GPIO2] = 7,
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[IRQ_GPIO3] = 7,
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[IRQ_GPIO4] = 7,
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[IRQ_GPIO5] = 7,
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[IRQ_GPIO6] = 7,
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[IRQ_GPIO7] = 7,
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[IRQ_GPIOBNK0] = 7,
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[IRQ_GPIOBNK1] = 7,
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[IRQ_GPIOBNK2] = 7,
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[IRQ_GPIOBNK3] = 7,
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[IRQ_GPIOBNK4] = 7,
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[IRQ_COMMTX] = 7,
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[IRQ_COMMRX] = 7,
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[IRQ_EMUINT] = 7,
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};
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/*----------------------------------------------------------------------*/
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static s8 queue_priority_mapping[][2] = {
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/* {event queue no, Priority} */
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{0, 3},
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{1, 7},
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{-1, -1},
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};
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static const struct dma_slave_map dm644x_edma_map[] = {
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{ "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
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{ "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
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{ "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
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{ "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
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{ "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
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{ "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
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};
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static struct edma_soc_info dm644x_edma_pdata = {
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.queue_priority_mapping = queue_priority_mapping,
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.default_queue = EVENTQ_1,
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.slave_map = dm644x_edma_map,
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.slavecnt = ARRAY_SIZE(dm644x_edma_map),
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};
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static struct resource edma_resources[] = {
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{
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.name = "edma3_cc",
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.start = 0x01c00000,
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.end = 0x01c00000 + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_tc0",
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.start = 0x01c10000,
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.end = 0x01c10000 + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_tc1",
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.start = 0x01c10400,
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.end = 0x01c10400 + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "edma3_ccint",
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.start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "edma3_ccerrint",
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.start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
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.flags = IORESOURCE_IRQ,
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},
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/* not using TC*_ERR */
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};
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static const struct platform_device_info dm644x_edma_device __initconst = {
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.name = "edma",
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.id = 0,
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.dma_mask = DMA_BIT_MASK(32),
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.res = edma_resources,
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.num_res = ARRAY_SIZE(edma_resources),
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.data = &dm644x_edma_pdata,
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.size_data = sizeof(dm644x_edma_pdata),
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};
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/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
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static struct resource dm644x_asp_resources[] = {
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{
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.name = "mpu",
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.start = DAVINCI_ASP0_BASE,
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.end = DAVINCI_ASP0_BASE + SZ_8K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = DAVINCI_DMA_ASP0_TX,
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.end = DAVINCI_DMA_ASP0_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = DAVINCI_DMA_ASP0_RX,
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.end = DAVINCI_DMA_ASP0_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device dm644x_asp_device = {
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.name = "davinci-mcbsp",
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.id = -1,
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.num_resources = ARRAY_SIZE(dm644x_asp_resources),
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.resource = dm644x_asp_resources,
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};
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#define DM644X_VPSS_BASE 0x01c73400
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static struct resource dm644x_vpss_resources[] = {
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{
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/* VPSS Base address */
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.name = "vpss",
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.start = DM644X_VPSS_BASE,
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.end = DM644X_VPSS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm644x_vpss_device = {
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.name = "vpss",
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.id = -1,
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.dev.platform_data = "dm644x_vpss",
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.num_resources = ARRAY_SIZE(dm644x_vpss_resources),
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.resource = dm644x_vpss_resources,
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};
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static struct resource dm644x_vpfe_resources[] = {
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{
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.start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
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.end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
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.end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
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static struct resource dm644x_ccdc_resource[] = {
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/* CCDC Base address */
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{
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.start = 0x01c70400,
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.end = 0x01c70400 + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm644x_ccdc_dev = {
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.name = "dm644x_ccdc",
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.id = -1,
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.num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
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.resource = dm644x_ccdc_resource,
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.dev = {
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.dma_mask = &dm644x_video_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct platform_device dm644x_vpfe_dev = {
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.name = CAPTURE_DRV_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
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.resource = dm644x_vpfe_resources,
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.dev = {
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.dma_mask = &dm644x_video_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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#define DM644X_OSD_BASE 0x01c72600
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static struct resource dm644x_osd_resources[] = {
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{
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.start = DM644X_OSD_BASE,
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.end = DM644X_OSD_BASE + 0x1ff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm644x_osd_dev = {
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.name = DM644X_VPBE_OSD_SUBDEV_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(dm644x_osd_resources),
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.resource = dm644x_osd_resources,
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.dev = {
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.dma_mask = &dm644x_video_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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#define DM644X_VENC_BASE 0x01c72400
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static struct resource dm644x_venc_resources[] = {
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{
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.start = DM644X_VENC_BASE,
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.end = DM644X_VENC_BASE + 0x17f,
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.flags = IORESOURCE_MEM,
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},
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};
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#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
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#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
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#define DM644X_VPSS_VENCLKEN BIT(3)
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#define DM644X_VPSS_DACCLKEN BIT(4)
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static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
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unsigned int pclock)
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{
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int ret = 0;
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u32 v = DM644X_VPSS_VENCLKEN;
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switch (type) {
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case VPBE_ENC_STD:
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v |= DM644X_VPSS_DACCLKEN;
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writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
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break;
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case VPBE_ENC_DV_TIMINGS:
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if (pclock <= 27000000) {
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v |= DM644X_VPSS_DACCLKEN;
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writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
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} else {
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/*
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* For HD, use external clock source since
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* HD requires higher clock rate
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*/
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v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
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writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
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}
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static struct resource dm644x_v4l2_disp_resources[] = {
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{
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.start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
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.end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dm644x_vpbe_display = {
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.name = "vpbe-v4l2",
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.id = -1,
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.num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
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.resource = dm644x_v4l2_disp_resources,
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.dev = {
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.dma_mask = &dm644x_video_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct venc_platform_data dm644x_venc_pdata = {
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.setup_clock = dm644x_venc_setup_clock,
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};
|
|
|
|
static struct platform_device dm644x_venc_dev = {
|
|
.name = DM644X_VPBE_VENC_SUBDEV_NAME,
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(dm644x_venc_resources),
|
|
.resource = dm644x_venc_resources,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &dm644x_venc_pdata,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_vpbe_dev = {
|
|
.name = "vpbe_controller",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &dm644x_video_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
static struct resource dm644_gpio_resources[] = {
|
|
{ /* registers */
|
|
.start = DAVINCI_GPIO_BASE,
|
|
.end = DAVINCI_GPIO_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{ /* interrupt */
|
|
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
.start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
|
|
.end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
|
|
.no_auto_base = true,
|
|
.base = 0,
|
|
.ngpio = 71,
|
|
};
|
|
|
|
int __init dm644x_gpio_register(void)
|
|
{
|
|
return davinci_gpio_register(dm644_gpio_resources,
|
|
ARRAY_SIZE(dm644_gpio_resources),
|
|
&dm644_gpio_platform_data);
|
|
}
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
static struct map_desc dm644x_io_desc[] = {
|
|
{
|
|
.virtual = IO_VIRT,
|
|
.pfn = __phys_to_pfn(IO_PHYS),
|
|
.length = IO_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
/* Contents of JTAG ID register used to identify exact cpu type */
|
|
static struct davinci_id dm644x_ids[] = {
|
|
{
|
|
.variant = 0x0,
|
|
.part_no = 0xb700,
|
|
.manufacturer = 0x017,
|
|
.cpu_id = DAVINCI_CPU_ID_DM6446,
|
|
.name = "dm6446",
|
|
},
|
|
{
|
|
.variant = 0x1,
|
|
.part_no = 0xb700,
|
|
.manufacturer = 0x017,
|
|
.cpu_id = DAVINCI_CPU_ID_DM6446,
|
|
.name = "dm6446a",
|
|
},
|
|
};
|
|
|
|
/*
|
|
* Bottom half of timer0 is used for clockevent, top half is used for
|
|
* clocksource.
|
|
*/
|
|
static const struct davinci_timer_cfg dm644x_timer_cfg = {
|
|
.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
|
|
.irq = {
|
|
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
|
|
DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
|
|
},
|
|
};
|
|
|
|
static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
|
|
{
|
|
.mapbase = DAVINCI_UART0_BASE,
|
|
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0,
|
|
}
|
|
};
|
|
static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
|
|
{
|
|
.mapbase = DAVINCI_UART1_BASE,
|
|
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0,
|
|
}
|
|
};
|
|
static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
|
|
{
|
|
.mapbase = DAVINCI_UART2_BASE,
|
|
.irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
|
|
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
|
|
UPF_IOREMAP,
|
|
.iotype = UPIO_MEM,
|
|
.regshift = 2,
|
|
},
|
|
{
|
|
.flags = 0,
|
|
}
|
|
};
|
|
|
|
struct platform_device dm644x_serial_device[] = {
|
|
{
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM,
|
|
.dev = {
|
|
.platform_data = dm644x_serial0_platform_data,
|
|
}
|
|
},
|
|
{
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM1,
|
|
.dev = {
|
|
.platform_data = dm644x_serial1_platform_data,
|
|
}
|
|
},
|
|
{
|
|
.name = "serial8250",
|
|
.id = PLAT8250_DEV_PLATFORM2,
|
|
.dev = {
|
|
.platform_data = dm644x_serial2_platform_data,
|
|
}
|
|
},
|
|
{
|
|
}
|
|
};
|
|
|
|
static const struct davinci_soc_info davinci_soc_info_dm644x = {
|
|
.io_desc = dm644x_io_desc,
|
|
.io_desc_num = ARRAY_SIZE(dm644x_io_desc),
|
|
.jtag_id_reg = 0x01c40028,
|
|
.ids = dm644x_ids,
|
|
.ids_num = ARRAY_SIZE(dm644x_ids),
|
|
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
|
|
.pinmux_pins = dm644x_pins,
|
|
.pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
|
|
.emac_pdata = &dm644x_emac_pdata,
|
|
.sram_dma = 0x00008000,
|
|
.sram_len = SZ_16K,
|
|
};
|
|
|
|
void __init dm644x_init_asp(void)
|
|
{
|
|
davinci_cfg_reg(DM644X_MCBSP);
|
|
platform_device_register(&dm644x_asp_device);
|
|
}
|
|
|
|
void __init dm644x_init(void)
|
|
{
|
|
davinci_common_init(&davinci_soc_info_dm644x);
|
|
davinci_map_sysmod();
|
|
}
|
|
|
|
void __init dm644x_init_time(void)
|
|
{
|
|
void __iomem *pll1, *psc;
|
|
struct clk *clk;
|
|
int rv;
|
|
|
|
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
|
|
|
|
pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
|
|
dm644x_pll1_init(NULL, pll1, NULL);
|
|
|
|
psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
|
|
dm644x_psc_init(NULL, psc);
|
|
|
|
clk = clk_get(NULL, "timer0");
|
|
if (WARN_ON(IS_ERR(clk))) {
|
|
pr_err("Unable to get the timer clock\n");
|
|
return;
|
|
}
|
|
|
|
rv = davinci_timer_register(clk, &dm644x_timer_cfg);
|
|
WARN(rv, "Unable to register the timer: %d\n", rv);
|
|
}
|
|
|
|
static struct resource dm644x_pll2_resources[] = {
|
|
{
|
|
.start = DAVINCI_PLL2_BASE,
|
|
.end = DAVINCI_PLL2_BASE + SZ_1K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dm644x_pll2_device = {
|
|
.name = "dm644x-pll2",
|
|
.id = -1,
|
|
.resource = dm644x_pll2_resources,
|
|
.num_resources = ARRAY_SIZE(dm644x_pll2_resources),
|
|
};
|
|
|
|
void __init dm644x_register_clocks(void)
|
|
{
|
|
/* PLL1 and PSC are registered in dm644x_init_time() */
|
|
platform_device_register(&dm644x_pll2_device);
|
|
}
|
|
|
|
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
|
|
struct vpbe_config *vpbe_cfg)
|
|
{
|
|
if (vpfe_cfg || vpbe_cfg)
|
|
platform_device_register(&dm644x_vpss_device);
|
|
|
|
if (vpfe_cfg) {
|
|
dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
|
|
platform_device_register(&dm644x_ccdc_dev);
|
|
platform_device_register(&dm644x_vpfe_dev);
|
|
}
|
|
|
|
if (vpbe_cfg) {
|
|
dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
|
|
platform_device_register(&dm644x_osd_dev);
|
|
platform_device_register(&dm644x_venc_dev);
|
|
platform_device_register(&dm644x_vpbe_dev);
|
|
platform_device_register(&dm644x_vpbe_display);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct davinci_aintc_config dm644x_aintc_config = {
|
|
.reg = {
|
|
.start = DAVINCI_ARM_INTC_BASE,
|
|
.end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
.num_irqs = 64,
|
|
.prios = dm644x_default_priorities,
|
|
};
|
|
|
|
void __init dm644x_init_irq(void)
|
|
{
|
|
davinci_aintc_init(&dm644x_aintc_config);
|
|
}
|
|
|
|
void __init dm644x_init_devices(void)
|
|
{
|
|
struct platform_device *edma_pdev;
|
|
int ret;
|
|
|
|
edma_pdev = platform_device_register_full(&dm644x_edma_device);
|
|
if (IS_ERR(edma_pdev))
|
|
pr_warn("%s: Failed to register eDMA\n", __func__);
|
|
|
|
platform_device_register(&dm644x_mdio_device);
|
|
platform_device_register(&dm644x_emac_device);
|
|
|
|
ret = davinci_init_wdt();
|
|
if (ret)
|
|
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
|
|
|
|
}
|