538 lines
20 KiB
C
538 lines
20 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU Geeral Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* James P. Ketrenos <ipw2100-admin@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef __iwlwifi_hw_h__
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#define __iwlwifi_hw_h__
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/*
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* This file defines hardware constants common to 3945 and 4965.
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*
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* Device-specific constants are defined in iwl-3945-hw.h and iwl-4965-hw.h,
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* although this file contains a few definitions for which the .c
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* implementation is the same for 3945 and 4965, except for the value of
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* a constant.
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*
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* uCode API constants are defined in iwl-commands.h.
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*
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* NOTE: DO NOT PUT OS IMPLEMENTATION-SPECIFIC DECLARATIONS HERE
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*
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* The iwl-*hw.h (and files they include) files should remain OS/driver
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* implementation independent, declaring only the hardware interface.
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*/
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/* uCode queue management definitions */
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#define IWL_CMD_QUEUE_NUM 4
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#define IWL_CMD_FIFO_NUM 4
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#define IWL_BACK_QUEUE_FIRST_ID 7
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/* Tx rates */
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#define IWL_CCK_RATES 4
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#define IWL_OFDM_RATES 8
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#if IWL == 3945
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#define IWL_HT_RATES 0
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#elif IWL == 4965
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#define IWL_HT_RATES 16
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#endif
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#define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
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/* Time constants */
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#define SHORT_SLOT_TIME 9
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#define LONG_SLOT_TIME 20
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/* RSSI to dBm */
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#if IWL == 3945
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#define IWL_RSSI_OFFSET 95
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#elif IWL == 4965
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#define IWL_RSSI_OFFSET 44
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#endif
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#include "iwl-eeprom.h"
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#include "iwl-commands.h"
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#define PCI_LINK_CTRL 0x0F0
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#define PCI_POWER_SOURCE 0x0C8
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#define PCI_REG_WUM8 0x0E8
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#define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
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/*=== CSR (control and status registers) ===*/
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#define CSR_BASE (0x000)
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#define CSR_SW_VER (CSR_BASE+0x000)
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#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
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#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
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#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
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#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
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#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
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#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
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#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
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#define CSR_GP_CNTRL (CSR_BASE+0x024)
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#define CSR_HW_REV (CSR_BASE+0x028)
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#define CSR_EEPROM_REG (CSR_BASE+0x02c)
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#define CSR_EEPROM_GP (CSR_BASE+0x030)
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#define CSR_GP_UCODE (CSR_BASE+0x044)
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#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
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#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
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#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
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#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
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#define CSR_LED_REG (CSR_BASE+0x094)
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#define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
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#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
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/* HW I/F configuration */
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#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
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#define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
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#define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
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#define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
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#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
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#define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
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#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
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/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
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* acknowledged (reset) by host writing "1" to flagged bits. */
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#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
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#define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */
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#define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */
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#define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */
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#define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
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#define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */
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#define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */
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#define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */
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#define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */
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#define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */
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#define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */
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#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
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CSR_INT_BIT_HW_ERR | \
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CSR_INT_BIT_FH_TX | \
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CSR_INT_BIT_SW_ERR | \
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CSR_INT_BIT_RF_KILL | \
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CSR_INT_BIT_SW_RX | \
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CSR_INT_BIT_WAKEUP | \
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CSR_INT_BIT_ALIVE)
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/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
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#define CSR_FH_INT_BIT_ERR (1<<31) /* Error */
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#define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */
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#define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
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#define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */
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#define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */
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#define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
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#define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */
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#define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */
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#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
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CSR_FH_INT_BIT_RX_CHNL2 | \
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CSR_FH_INT_BIT_RX_CHNL1 | \
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CSR_FH_INT_BIT_RX_CHNL0)
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#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
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CSR_FH_INT_BIT_TX_CHNL1 | \
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CSR_FH_INT_BIT_TX_CHNL0 )
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/* RESET */
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#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
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#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
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#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
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#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
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#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
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/* GP (general purpose) CONTROL */
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#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
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#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
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#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
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#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
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#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
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#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
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#define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
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#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
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/* EEPROM REG */
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#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
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#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
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/* EEPROM GP */
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#define CSR_EEPROM_GP_VALID_MSK (0x00000006)
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#define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
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#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
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/* UCODE DRV GP */
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#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
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#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
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#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
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#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
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/* GPIO */
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#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
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#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
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#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
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/* GI Chicken Bits */
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
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#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
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/* CSR_ANA_PLL_CFG */
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#define CSR_ANA_PLL_CFG_SH (0x00880300)
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#define CSR_LED_REG_TRUN_ON (0x00000078)
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#define CSR_LED_REG_TRUN_OFF (0x00000038)
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#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
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/* DRAM_INT_TBL_CTRL */
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#define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
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#define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
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/*=== HBUS (Host-side Bus) ===*/
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#define HBUS_BASE (0x400)
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#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
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#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
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#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
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#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
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#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
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#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
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#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
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#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
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#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
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#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
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/* SCD (Scheduler) */
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#define SCD_BASE (CSR_BASE + 0x2E00)
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#define SCD_MODE_REG (SCD_BASE + 0x000)
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#define SCD_ARASTAT_REG (SCD_BASE + 0x004)
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#define SCD_TXFACT_REG (SCD_BASE + 0x010)
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#define SCD_TXF4MF_REG (SCD_BASE + 0x014)
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#define SCD_TXF5MF_REG (SCD_BASE + 0x020)
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#define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
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#define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
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/*=== FH (data Flow Handler) ===*/
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#define FH_BASE (0x800)
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#define FH_CBCC_TABLE (FH_BASE+0x140)
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#define FH_TFDB_TABLE (FH_BASE+0x180)
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#define FH_RCSR_TABLE (FH_BASE+0x400)
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#define FH_RSSR_TABLE (FH_BASE+0x4c0)
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#define FH_TCSR_TABLE (FH_BASE+0x500)
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#define FH_TSSR_TABLE (FH_BASE+0x680)
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/* TFDB (Transmit Frame Buffer Descriptor) */
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#define FH_TFDB(_channel, buf) \
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(FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
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#define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
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(FH_TFDB_TABLE + 0x50 * _channel)
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/* CBCC _channel is [0,2] */
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#define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
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#define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
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#define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
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/* RCSR _channel is [0,2] */
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#define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
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#define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
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#define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
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#define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
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#define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
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#if IWL == 3945
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#define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
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#elif IWL == 4965
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#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
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#endif
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/* RSSR */
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#define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
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#define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
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/* TCSR */
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#define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
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#define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
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#define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
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#define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
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/* TSSR */
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#define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
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#define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
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#define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
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/* 18 - reserved */
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/* card static random access memory (SRAM) for processor data and instructs */
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#define RTC_INST_LOWER_BOUND (0x000000)
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#define RTC_DATA_LOWER_BOUND (0x800000)
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/* DBM */
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#define ALM_FH_SRVC_CHNL (6)
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#define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
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#define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
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#define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
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#define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
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#define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
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#define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
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#define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
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#define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
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((1LU << _channel) << 24)
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#define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
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((1LU << _channel) << 16)
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#define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
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(ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
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ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
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#define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
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#define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
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#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
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#define TFD_QUEUE_MIN 0
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#define TFD_QUEUE_MAX 6
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#define TFD_QUEUE_SIZE_MAX (256)
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/* spectrum and channel data structures */
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#define IWL_NUM_SCAN_RATES (2)
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#define IWL_SCAN_FLAG_24GHZ (1<<0)
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#define IWL_SCAN_FLAG_52GHZ (1<<1)
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#define IWL_SCAN_FLAG_ACTIVE (1<<2)
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#define IWL_SCAN_FLAG_DIRECT (1<<3)
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#define IWL_MAX_CMD_SIZE 1024
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#define IWL_DEFAULT_TX_RETRY 15
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#define IWL_MAX_TX_RETRY 16
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/*********************************************/
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#define RFD_SIZE 4
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#define NUM_TFD_CHUNKS 4
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#define RX_QUEUE_SIZE 256
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#define RX_QUEUE_MASK 255
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#define RX_QUEUE_SIZE_LOG 8
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/* QoS definitions */
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#define CW_MIN_OFDM 15
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#define CW_MAX_OFDM 1023
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#define CW_MIN_CCK 31
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#define CW_MAX_CCK 1023
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#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
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#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
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#define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
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#define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
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#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
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#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
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#define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
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#define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
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#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
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#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
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#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
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#define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
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#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
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#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
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#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
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#define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
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#define QOS_TX0_AIFS 3
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#define QOS_TX1_AIFS 7
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#define QOS_TX2_AIFS 2
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#define QOS_TX3_AIFS 2
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#define QOS_TX0_ACM 0
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#define QOS_TX1_ACM 0
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#define QOS_TX2_ACM 0
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#define QOS_TX3_ACM 0
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#define QOS_TX0_TXOP_LIMIT_CCK 0
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#define QOS_TX1_TXOP_LIMIT_CCK 0
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#define QOS_TX2_TXOP_LIMIT_CCK 6016
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#define QOS_TX3_TXOP_LIMIT_CCK 3264
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#define QOS_TX0_TXOP_LIMIT_OFDM 0
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#define QOS_TX1_TXOP_LIMIT_OFDM 0
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#define QOS_TX2_TXOP_LIMIT_OFDM 3008
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#define QOS_TX3_TXOP_LIMIT_OFDM 1504
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#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
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#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
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#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
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#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
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#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
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#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
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|
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#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
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#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
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#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
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#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
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|
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#define DEF_TX0_AIFS (2)
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#define DEF_TX1_AIFS (2)
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#define DEF_TX2_AIFS (2)
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#define DEF_TX3_AIFS (2)
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#define DEF_TX0_ACM 0
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#define DEF_TX1_ACM 0
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#define DEF_TX2_ACM 0
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#define DEF_TX3_ACM 0
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#define DEF_TX0_TXOP_LIMIT_CCK 0
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#define DEF_TX1_TXOP_LIMIT_CCK 0
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#define DEF_TX2_TXOP_LIMIT_CCK 0
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#define DEF_TX3_TXOP_LIMIT_CCK 0
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#define DEF_TX0_TXOP_LIMIT_OFDM 0
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#define DEF_TX1_TXOP_LIMIT_OFDM 0
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#define DEF_TX2_TXOP_LIMIT_OFDM 0
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#define DEF_TX3_TXOP_LIMIT_OFDM 0
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|
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#define QOS_QOS_SETS 3
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#define QOS_PARAM_SET_ACTIVE 0
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#define QOS_PARAM_SET_DEF_CCK 1
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#define QOS_PARAM_SET_DEF_OFDM 2
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|
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#define CTRL_QOS_NO_ACK (0x0020)
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#define DCT_FLAG_EXT_QOS_ENABLED (0x10)
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|
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#define U32_PAD(n) ((4-(n))&0x3)
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|
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/*
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* Generic queue structure
|
|
*
|
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* Contains common data for Rx and Tx queues
|
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*/
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#define TFD_CTL_COUNT_SET(n) (n<<24)
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#define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7)
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#define TFD_CTL_PAD_SET(n) (n<<28)
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#define TFD_CTL_PAD_GET(ctl) (ctl>>28)
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|
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#define TFD_TX_CMD_SLOTS 256
|
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#define TFD_CMD_SLOTS 32
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|
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#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
|
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sizeof(struct iwl_cmd_meta))
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|
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/*
|
|
* RX related structures and functions
|
|
*/
|
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#define RX_FREE_BUFFERS 64
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#define RX_LOW_WATERMARK 8
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#endif /* __iwlwifi_hw_h__ */
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