237 lines
6.6 KiB
C
237 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright IBM Corp. 2016
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*
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* Adjunct processor bus inline assemblies.
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*/
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#ifndef _AP_ASM_H_
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#define _AP_ASM_H_
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#include <asm/isc.h>
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/**
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* ap_intructions_available() - Test if AP instructions are available.
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*
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* Returns 0 if the AP instructions are installed.
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*/
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static inline int ap_instructions_available(void)
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{
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register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
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register unsigned long reg1 asm ("1") = -ENODEV;
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register unsigned long reg2 asm ("2") = 0UL;
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asm volatile(
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" .long 0xb2af0000\n" /* PQAP(TAPQ) */
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"0: la %1,0\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: "+d" (reg0), "+d" (reg1), "+d" (reg2) : : "cc");
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return reg1;
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}
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/**
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* ap_tapq(): Test adjunct processor queue.
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* @qid: The AP queue number
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* @info: Pointer to queue descriptor
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
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{
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register unsigned long reg0 asm ("0") = qid;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2") = 0UL;
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asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */
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: "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
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if (info)
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*info = reg2;
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return reg1;
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}
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/**
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* ap_pqap_rapq(): Reset adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
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{
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register unsigned long reg0 asm ("0") = qid | 0x01000000UL;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2") = 0UL;
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asm volatile(
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".long 0xb2af0000" /* PQAP(RAPQ) */
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: "+d" (reg0), "=d" (reg1), "+d" (reg2) : : "cc");
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return reg1;
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}
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/**
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* ap_aqic(): Control interruption for a specific AP.
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* @qid: The AP queue number
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* @qirqctrl: struct ap_qirq_ctrl (64 bit value)
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* @ind: The notification indicator byte
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*
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* Returns AP queue status.
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*/
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static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
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struct ap_qirq_ctrl qirqctrl,
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void *ind)
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{
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register unsigned long reg0 asm ("0") = qid | (3UL << 24);
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register struct ap_qirq_ctrl reg1_in asm ("1") = qirqctrl;
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register struct ap_queue_status reg1_out asm ("1");
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register void *reg2 asm ("2") = ind;
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asm volatile(
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".long 0xb2af0000" /* PQAP(AQIC) */
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: "+d" (reg0), "+d" (reg1_in), "=d" (reg1_out), "+d" (reg2)
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:
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: "cc");
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return reg1_out;
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}
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/**
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* ap_qci(): Get AP configuration data
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*
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* Returns 0 on success, or -EOPNOTSUPP.
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*/
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static inline int ap_qci(void *config)
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{
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register unsigned long reg0 asm ("0") = 0x04000000UL;
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register unsigned long reg1 asm ("1") = -EINVAL;
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register void *reg2 asm ("2") = (void *) config;
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asm volatile(
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".long 0xb2af0000\n" /* PQAP(QCI) */
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"0: la %1,0\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: "+d" (reg0), "+d" (reg1), "+d" (reg2)
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:
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: "cc", "memory");
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return reg1;
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}
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/*
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* union ap_qact_ap_info - used together with the
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* ap_aqic() function to provide a convenient way
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* to handle the ap info needed by the qact function.
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*/
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union ap_qact_ap_info {
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unsigned long val;
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struct {
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unsigned int : 3;
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unsigned int mode : 3;
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unsigned int : 26;
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unsigned int cat : 8;
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unsigned int : 8;
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unsigned char ver[2];
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};
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};
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/**
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* ap_qact(): Query AP combatibility type.
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* @qid: The AP queue number
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* @apinfo: On input the info about the AP queue. On output the
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* alternate AP queue info provided by the qact function
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* in GR2 is stored in.
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*
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* Returns AP queue status. Check response_code field for failures.
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*/
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static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
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union ap_qact_ap_info *apinfo)
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{
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register unsigned long reg0 asm ("0") = qid | (5UL << 24)
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| ((ifbit & 0x01) << 22);
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register unsigned long reg1_in asm ("1") = apinfo->val;
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register struct ap_queue_status reg1_out asm ("1");
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register unsigned long reg2 asm ("2") = 0;
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asm volatile(
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".long 0xb2af0000" /* PQAP(QACT) */
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: "+d" (reg0), "+d" (reg1_in), "=d" (reg1_out), "+d" (reg2)
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: : "cc");
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apinfo->val = reg2;
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return reg1_out;
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}
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/**
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* ap_nqap(): Send message to adjunct processor queue.
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* @qid: The AP queue number
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* @psmid: The program supplied message identifier
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* @msg: The message text
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* @length: The message length
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*
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* Returns AP queue status structure.
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* Condition code 1 on NQAP can't happen because the L bit is 1.
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* Condition code 2 on NQAP also means the send is incomplete,
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* because a segment boundary was reached. The NQAP is repeated.
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*/
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static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
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unsigned long long psmid,
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void *msg, size_t length)
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{
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register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2") = (unsigned long) msg;
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register unsigned long reg3 asm ("3") = (unsigned long) length;
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register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
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register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
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asm volatile (
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"0: .long 0xb2ad0042\n" /* NQAP */
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" brc 2,0b"
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: "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
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: "d" (reg4), "d" (reg5)
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: "cc", "memory");
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return reg1;
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}
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/**
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* ap_dqap(): Receive message from adjunct processor queue.
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* @qid: The AP queue number
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* @psmid: Pointer to program supplied message identifier
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* @msg: The message text
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* @length: The message length
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*
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* Returns AP queue status structure.
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* Condition code 1 on DQAP means the receive has taken place
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* but only partially. The response is incomplete, hence the
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* DQAP is repeated.
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* Condition code 2 on DQAP also means the receive is incomplete,
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* this time because a segment boundary was reached. Again, the
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* DQAP is repeated.
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* Note that gpr2 is used by the DQAP instruction to keep track of
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* any 'residual' length, in case the instruction gets interrupted.
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* Hence it gets zeroed before the instruction.
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*/
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static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
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unsigned long long *psmid,
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void *msg, size_t length)
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{
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register unsigned long reg0 asm("0") = qid | 0x80000000UL;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm("2") = 0UL;
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register unsigned long reg4 asm("4") = (unsigned long) msg;
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register unsigned long reg5 asm("5") = (unsigned long) length;
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register unsigned long reg6 asm("6") = 0UL;
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register unsigned long reg7 asm("7") = 0UL;
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asm volatile(
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"0: .long 0xb2ae0064\n" /* DQAP */
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" brc 6,0b\n"
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: "+d" (reg0), "=d" (reg1), "+d" (reg2),
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"+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
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: : "cc", "memory");
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*psmid = (((unsigned long long) reg6) << 32) + reg7;
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return reg1;
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}
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#endif /* _AP_ASM_H_ */
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