578 lines
15 KiB
C
578 lines
15 KiB
C
/*
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* GPIO driver for LPC32xx SoC
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/gpio.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/platform_data/gpio-lpc32xx.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <mach/irqs.h>
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#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
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#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
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#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
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#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
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#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
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#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
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#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
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#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
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#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
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#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
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#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
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#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
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#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
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#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
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#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
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#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
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#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
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#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
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#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
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#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
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#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
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#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
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#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
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#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
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#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
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#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
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#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
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#define GPIO012_PIN_TO_BIT(x) (1 << (x))
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#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
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#define GPO3_PIN_TO_BIT(x) (1 << (x))
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#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
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#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
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#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
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#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
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#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
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#define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
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struct gpio_regs {
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void __iomem *inp_state;
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void __iomem *outp_state;
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void __iomem *outp_set;
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void __iomem *outp_clr;
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void __iomem *dir_set;
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void __iomem *dir_clr;
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};
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/*
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* GPIO names
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*/
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static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
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"p0.0", "p0.1", "p0.2", "p0.3",
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"p0.4", "p0.5", "p0.6", "p0.7"
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};
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static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
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"p1.0", "p1.1", "p1.2", "p1.3",
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"p1.4", "p1.5", "p1.6", "p1.7",
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"p1.8", "p1.9", "p1.10", "p1.11",
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"p1.12", "p1.13", "p1.14", "p1.15",
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"p1.16", "p1.17", "p1.18", "p1.19",
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"p1.20", "p1.21", "p1.22", "p1.23",
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};
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static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
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"p2.0", "p2.1", "p2.2", "p2.3",
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"p2.4", "p2.5", "p2.6", "p2.7",
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"p2.8", "p2.9", "p2.10", "p2.11",
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"p2.12"
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};
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static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
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"gpio00", "gpio01", "gpio02", "gpio03",
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"gpio04", "gpio05"
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};
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static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
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"gpi00", "gpi01", "gpi02", "gpi03",
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"gpi04", "gpi05", "gpi06", "gpi07",
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"gpi08", "gpi09", NULL, NULL,
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NULL, NULL, NULL, "gpi15",
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"gpi16", "gpi17", "gpi18", "gpi19",
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"gpi20", "gpi21", "gpi22", "gpi23",
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"gpi24", "gpi25", "gpi26", "gpi27",
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"gpi28"
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};
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static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
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"gpo00", "gpo01", "gpo02", "gpo03",
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"gpo04", "gpo05", "gpo06", "gpo07",
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"gpo08", "gpo09", "gpo10", "gpo11",
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"gpo12", "gpo13", "gpo14", "gpo15",
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"gpo16", "gpo17", "gpo18", "gpo19",
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"gpo20", "gpo21", "gpo22", "gpo23"
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};
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static struct gpio_regs gpio_grp_regs_p0 = {
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.inp_state = LPC32XX_GPIO_P0_INP_STATE,
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.outp_set = LPC32XX_GPIO_P0_OUTP_SET,
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.outp_clr = LPC32XX_GPIO_P0_OUTP_CLR,
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.dir_set = LPC32XX_GPIO_P0_DIR_SET,
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.dir_clr = LPC32XX_GPIO_P0_DIR_CLR,
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};
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static struct gpio_regs gpio_grp_regs_p1 = {
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.inp_state = LPC32XX_GPIO_P1_INP_STATE,
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.outp_set = LPC32XX_GPIO_P1_OUTP_SET,
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.outp_clr = LPC32XX_GPIO_P1_OUTP_CLR,
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.dir_set = LPC32XX_GPIO_P1_DIR_SET,
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.dir_clr = LPC32XX_GPIO_P1_DIR_CLR,
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};
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static struct gpio_regs gpio_grp_regs_p2 = {
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.inp_state = LPC32XX_GPIO_P2_INP_STATE,
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.outp_set = LPC32XX_GPIO_P2_OUTP_SET,
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.outp_clr = LPC32XX_GPIO_P2_OUTP_CLR,
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.dir_set = LPC32XX_GPIO_P2_DIR_SET,
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.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
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};
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static struct gpio_regs gpio_grp_regs_p3 = {
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.inp_state = LPC32XX_GPIO_P3_INP_STATE,
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.outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
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.outp_set = LPC32XX_GPIO_P3_OUTP_SET,
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.outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
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.dir_set = LPC32XX_GPIO_P2_DIR_SET,
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.dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
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};
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struct lpc32xx_gpio_chip {
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struct gpio_chip chip;
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struct gpio_regs *gpio_grp;
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};
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static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
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struct gpio_chip *gpc)
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{
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return container_of(gpc, struct lpc32xx_gpio_chip, chip);
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}
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static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
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unsigned pin, int input)
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{
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if (input)
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__raw_writel(GPIO012_PIN_TO_BIT(pin),
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group->gpio_grp->dir_clr);
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else
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__raw_writel(GPIO012_PIN_TO_BIT(pin),
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group->gpio_grp->dir_set);
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}
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static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
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unsigned pin, int input)
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{
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u32 u = GPIO3_PIN_TO_BIT(pin);
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if (input)
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__raw_writel(u, group->gpio_grp->dir_clr);
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else
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__raw_writel(u, group->gpio_grp->dir_set);
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}
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static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
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unsigned pin, int high)
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{
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if (high)
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__raw_writel(GPIO012_PIN_TO_BIT(pin),
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group->gpio_grp->outp_set);
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else
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__raw_writel(GPIO012_PIN_TO_BIT(pin),
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group->gpio_grp->outp_clr);
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}
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static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
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unsigned pin, int high)
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{
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u32 u = GPIO3_PIN_TO_BIT(pin);
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if (high)
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__raw_writel(u, group->gpio_grp->outp_set);
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else
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__raw_writel(u, group->gpio_grp->outp_clr);
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}
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static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
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unsigned pin, int high)
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{
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if (high)
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__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
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else
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__raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
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}
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static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
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unsigned pin)
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{
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return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
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pin);
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}
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static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
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unsigned pin)
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{
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int state = __raw_readl(group->gpio_grp->inp_state);
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/*
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* P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
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* to bits 10..14, while GPIOP3-5 is mapped to bit 24.
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*/
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return GPIO3_PIN_IN_SEL(state, pin);
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}
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static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
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unsigned pin)
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{
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return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
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}
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static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
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unsigned pin)
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{
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return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
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}
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/*
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* GPIO primitives.
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*/
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static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
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unsigned pin)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpio_dir_p012(group, pin, 1);
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return 0;
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}
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static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
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unsigned pin)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpio_dir_p3(group, pin, 1);
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return 0;
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}
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static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
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unsigned pin)
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{
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return 0;
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}
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static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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return __get_gpio_state_p012(group, pin);
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}
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static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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return __get_gpio_state_p3(group, pin);
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}
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static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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return __get_gpi_state_p3(group, pin);
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}
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static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpio_level_p012(group, pin, value);
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__set_gpio_dir_p012(group, pin, 0);
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return 0;
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}
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static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpio_level_p3(group, pin, value);
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__set_gpio_dir_p3(group, pin, 0);
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return 0;
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}
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static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpo_level_p3(group, pin, value);
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return 0;
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}
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static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpio_level_p012(group, pin, value);
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}
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static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpio_level_p3(group, pin, value);
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}
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static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
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int value)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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__set_gpo_level_p3(group, pin, value);
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}
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static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
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{
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struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
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return __get_gpo_state_p3(group, pin);
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}
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static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
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{
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if (pin < chip->ngpio)
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return 0;
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return -EINVAL;
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}
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static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
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{
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return IRQ_LPC32XX_P0_P1_IRQ;
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}
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static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
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IRQ_LPC32XX_GPIO_00,
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IRQ_LPC32XX_GPIO_01,
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IRQ_LPC32XX_GPIO_02,
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IRQ_LPC32XX_GPIO_03,
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IRQ_LPC32XX_GPIO_04,
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IRQ_LPC32XX_GPIO_05,
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};
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static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
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{
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if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
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return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
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return -ENXIO;
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}
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static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
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IRQ_LPC32XX_GPI_00,
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IRQ_LPC32XX_GPI_01,
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IRQ_LPC32XX_GPI_02,
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IRQ_LPC32XX_GPI_03,
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IRQ_LPC32XX_GPI_04,
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IRQ_LPC32XX_GPI_05,
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IRQ_LPC32XX_GPI_06,
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IRQ_LPC32XX_GPI_07,
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IRQ_LPC32XX_GPI_08,
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IRQ_LPC32XX_GPI_09,
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-ENXIO, /* 10 */
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-ENXIO, /* 11 */
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-ENXIO, /* 12 */
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-ENXIO, /* 13 */
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-ENXIO, /* 14 */
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-ENXIO, /* 15 */
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-ENXIO, /* 16 */
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-ENXIO, /* 17 */
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-ENXIO, /* 18 */
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IRQ_LPC32XX_GPI_19,
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-ENXIO, /* 20 */
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-ENXIO, /* 21 */
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-ENXIO, /* 22 */
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-ENXIO, /* 23 */
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-ENXIO, /* 24 */
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-ENXIO, /* 25 */
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-ENXIO, /* 26 */
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-ENXIO, /* 27 */
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IRQ_LPC32XX_GPI_28,
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};
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static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
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{
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if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
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return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
|
|
return -ENXIO;
|
|
}
|
|
|
|
static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
|
|
{
|
|
.chip = {
|
|
.label = "gpio_p0",
|
|
.direction_input = lpc32xx_gpio_dir_input_p012,
|
|
.get = lpc32xx_gpio_get_value_p012,
|
|
.direction_output = lpc32xx_gpio_dir_output_p012,
|
|
.set = lpc32xx_gpio_set_value_p012,
|
|
.request = lpc32xx_gpio_request,
|
|
.to_irq = lpc32xx_gpio_to_irq_p01,
|
|
.base = LPC32XX_GPIO_P0_GRP,
|
|
.ngpio = LPC32XX_GPIO_P0_MAX,
|
|
.names = gpio_p0_names,
|
|
.can_sleep = false,
|
|
},
|
|
.gpio_grp = &gpio_grp_regs_p0,
|
|
},
|
|
{
|
|
.chip = {
|
|
.label = "gpio_p1",
|
|
.direction_input = lpc32xx_gpio_dir_input_p012,
|
|
.get = lpc32xx_gpio_get_value_p012,
|
|
.direction_output = lpc32xx_gpio_dir_output_p012,
|
|
.set = lpc32xx_gpio_set_value_p012,
|
|
.request = lpc32xx_gpio_request,
|
|
.to_irq = lpc32xx_gpio_to_irq_p01,
|
|
.base = LPC32XX_GPIO_P1_GRP,
|
|
.ngpio = LPC32XX_GPIO_P1_MAX,
|
|
.names = gpio_p1_names,
|
|
.can_sleep = false,
|
|
},
|
|
.gpio_grp = &gpio_grp_regs_p1,
|
|
},
|
|
{
|
|
.chip = {
|
|
.label = "gpio_p2",
|
|
.direction_input = lpc32xx_gpio_dir_input_p012,
|
|
.get = lpc32xx_gpio_get_value_p012,
|
|
.direction_output = lpc32xx_gpio_dir_output_p012,
|
|
.set = lpc32xx_gpio_set_value_p012,
|
|
.request = lpc32xx_gpio_request,
|
|
.base = LPC32XX_GPIO_P2_GRP,
|
|
.ngpio = LPC32XX_GPIO_P2_MAX,
|
|
.names = gpio_p2_names,
|
|
.can_sleep = false,
|
|
},
|
|
.gpio_grp = &gpio_grp_regs_p2,
|
|
},
|
|
{
|
|
.chip = {
|
|
.label = "gpio_p3",
|
|
.direction_input = lpc32xx_gpio_dir_input_p3,
|
|
.get = lpc32xx_gpio_get_value_p3,
|
|
.direction_output = lpc32xx_gpio_dir_output_p3,
|
|
.set = lpc32xx_gpio_set_value_p3,
|
|
.request = lpc32xx_gpio_request,
|
|
.to_irq = lpc32xx_gpio_to_irq_gpio_p3,
|
|
.base = LPC32XX_GPIO_P3_GRP,
|
|
.ngpio = LPC32XX_GPIO_P3_MAX,
|
|
.names = gpio_p3_names,
|
|
.can_sleep = false,
|
|
},
|
|
.gpio_grp = &gpio_grp_regs_p3,
|
|
},
|
|
{
|
|
.chip = {
|
|
.label = "gpi_p3",
|
|
.direction_input = lpc32xx_gpio_dir_in_always,
|
|
.get = lpc32xx_gpi_get_value,
|
|
.request = lpc32xx_gpio_request,
|
|
.to_irq = lpc32xx_gpio_to_irq_gpi_p3,
|
|
.base = LPC32XX_GPI_P3_GRP,
|
|
.ngpio = LPC32XX_GPI_P3_MAX,
|
|
.names = gpi_p3_names,
|
|
.can_sleep = false,
|
|
},
|
|
.gpio_grp = &gpio_grp_regs_p3,
|
|
},
|
|
{
|
|
.chip = {
|
|
.label = "gpo_p3",
|
|
.direction_output = lpc32xx_gpio_dir_out_always,
|
|
.set = lpc32xx_gpo_set_value,
|
|
.get = lpc32xx_gpo_get_value,
|
|
.request = lpc32xx_gpio_request,
|
|
.base = LPC32XX_GPO_P3_GRP,
|
|
.ngpio = LPC32XX_GPO_P3_MAX,
|
|
.names = gpo_p3_names,
|
|
.can_sleep = false,
|
|
},
|
|
.gpio_grp = &gpio_grp_regs_p3,
|
|
},
|
|
};
|
|
|
|
static int lpc32xx_of_xlate(struct gpio_chip *gc,
|
|
const struct of_phandle_args *gpiospec, u32 *flags)
|
|
{
|
|
/* Is this the correct bank? */
|
|
u32 bank = gpiospec->args[0];
|
|
if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
|
|
(gc != &lpc32xx_gpiochip[bank].chip)))
|
|
return -EINVAL;
|
|
|
|
if (flags)
|
|
*flags = gpiospec->args[2];
|
|
return gpiospec->args[1];
|
|
}
|
|
|
|
static int lpc32xx_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
|
|
if (pdev->dev.of_node) {
|
|
lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
|
|
lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
|
|
lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
|
|
}
|
|
gpiochip_add(&lpc32xx_gpiochip[i].chip);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id lpc32xx_gpio_of_match[] = {
|
|
{ .compatible = "nxp,lpc3220-gpio", },
|
|
{ },
|
|
};
|
|
#endif
|
|
|
|
static struct platform_driver lpc32xx_gpio_driver = {
|
|
.driver = {
|
|
.name = "lpc32xx-gpio",
|
|
.of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
|
|
},
|
|
.probe = lpc32xx_gpio_probe,
|
|
};
|
|
|
|
module_platform_driver(lpc32xx_gpio_driver);
|