102 lines
3.3 KiB
C
102 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef __ASM_TLB_MMU_V1_H__
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#define __ASM_TLB_MMU_V1_H__
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#include <asm/mmu.h>
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#if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)
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.macro TLB_WRITE_HEURISTICS
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#define JH_HACK1
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#undef JH_HACK2
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#undef JH_HACK3
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#ifdef JH_HACK3
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; Calculate set index for 2-way MMU
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; -avoiding use of GetIndex from MMU
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; and its unpleasant LFSR pseudo-random sequence
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;
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; r1 = TLBPD0 from TLB_RELOAD above
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;
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; -- jh_ex_way_set not cleared on startup
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; didn't want to change setup.c
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; hence extra instruction to clean
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;
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; -- should be in cache since in same line
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; as r0/r1 saves above
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;
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ld r0,[jh_ex_way_sel] ; victim pointer
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and r0,r0,1 ; clean
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xor.f r0,r0,1 ; flip
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st r0,[jh_ex_way_sel] ; store back
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asr r0,r1,12 ; get set # <<1, note bit 12=R=0
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or.nz r0,r0,1 ; set way bit
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and r0,r0,0xff ; clean
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sr r0,[ARC_REG_TLBINDEX]
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#endif
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#ifdef JH_HACK2
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; JH hack #2
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; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
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; Slower in thrash case (where it matters) because more code is executed
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; Inefficient due to two-register paradigm of this miss handler
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;
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/* r1 = data TLBPD0 at this point */
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lr r0,[eret] /* instruction address */
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xor r0,r0,r1 /* compare set # */
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and.f r0,r0,0x000fe000 /* 2-way MMU mask */
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bne 88f /* not in same set - no need to probe */
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lr r0,[eret] /* instruction address */
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and r0,r0,PAGE_MASK /* VPN of instruction address */
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; lr r1,[ARC_REG_TLBPD0] /* Data VPN+ASID - already in r1 from TLB_RELOAD*/
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and r1,r1,0xff /* Data ASID */
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or r0,r0,r1 /* Instruction address + Data ASID */
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lr r1,[ARC_REG_TLBPD0] /* save TLBPD0 containing data TLB*/
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sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
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sr TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
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lr r0,[ARC_REG_TLBINDEX] /* r0 = index where instruction is, if at all */
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sr r1,[ARC_REG_TLBPD0] /* restore TLBPD0 */
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xor r0,r0,1 /* flip bottom bit of data index */
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b.d 89f
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sr r0,[ARC_REG_TLBINDEX] /* and put it back */
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88:
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sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
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89:
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#endif
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#ifdef JH_HACK1
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;
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; Always checks whether instruction will be kicked out by dtlb miss
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;
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mov_s r3, r1 ; save PD0 prepared by TLB_RELOAD in r3
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lr r0,[eret] /* instruction address */
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and r0,r0,PAGE_MASK /* VPN of instruction address */
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bmsk r1,r3,7 /* Data ASID, bits 7-0 */
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or_s r0,r0,r1 /* Instruction address + Data ASID */
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sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
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sr TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
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lr r0,[ARC_REG_TLBINDEX] /* r0 = index where instruction is, if at all */
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sr r3,[ARC_REG_TLBPD0] /* restore TLBPD0 */
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sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
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lr r1,[ARC_REG_TLBINDEX] /* r1 = index where MMU wants to put data */
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cmp r0,r1 /* if no match on indices, go around */
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xor.eq r1,r1,1 /* flip bottom bit of data index */
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sr r1,[ARC_REG_TLBINDEX] /* and put it back */
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#endif
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.endm
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#endif
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#endif
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