342 lines
8.8 KiB
C
342 lines
8.8 KiB
C
#include "drmP.h"
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#include "nouveau_drv.h"
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#include <linux/pagemap.h>
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#include <linux/slab.h>
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#define NV_CTXDMA_PAGE_SHIFT 12
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#define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT)
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#define NV_CTXDMA_PAGE_MASK (NV_CTXDMA_PAGE_SIZE - 1)
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struct nouveau_sgdma_be {
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struct ttm_backend backend;
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struct drm_device *dev;
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dma_addr_t *pages;
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unsigned nr_pages;
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unsigned pte_start;
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bool bound;
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};
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static int
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nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
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struct page **pages, struct page *dummy_read_page)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev = nvbe->dev;
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NV_DEBUG(nvbe->dev, "num_pages = %ld\n", num_pages);
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if (nvbe->pages)
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return -EINVAL;
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nvbe->pages = kmalloc(sizeof(dma_addr_t) * num_pages, GFP_KERNEL);
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if (!nvbe->pages)
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return -ENOMEM;
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nvbe->nr_pages = 0;
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while (num_pages--) {
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nvbe->pages[nvbe->nr_pages] =
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pci_map_page(dev->pdev, pages[nvbe->nr_pages], 0,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev,
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nvbe->pages[nvbe->nr_pages])) {
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be->func->clear(be);
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return -EFAULT;
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}
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nvbe->nr_pages++;
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}
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return 0;
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}
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static void
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nouveau_sgdma_clear(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev;
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if (nvbe && nvbe->pages) {
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dev = nvbe->dev;
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NV_DEBUG(dev, "\n");
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if (nvbe->bound)
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be->func->unbind(be);
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while (nvbe->nr_pages--) {
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pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages],
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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}
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kfree(nvbe->pages);
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nvbe->pages = NULL;
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nvbe->nr_pages = 0;
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}
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}
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static inline unsigned
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nouveau_sgdma_pte(struct drm_device *dev, uint64_t offset)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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unsigned pte = (offset >> NV_CTXDMA_PAGE_SHIFT);
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if (dev_priv->card_type < NV_50)
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return pte + 2;
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return pte << 1;
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}
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static int
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nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev = nvbe->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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unsigned i, j, pte;
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NV_DEBUG(dev, "pg=0x%lx\n", mem->mm_node->start);
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dev_priv->engine.instmem.prepare_access(nvbe->dev, true);
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pte = nouveau_sgdma_pte(nvbe->dev, mem->mm_node->start << PAGE_SHIFT);
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nvbe->pte_start = pte;
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for (i = 0; i < nvbe->nr_pages; i++) {
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dma_addr_t dma_offset = nvbe->pages[i];
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uint32_t offset_l = lower_32_bits(dma_offset);
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uint32_t offset_h = upper_32_bits(dma_offset);
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for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++) {
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if (dev_priv->card_type < NV_50)
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nv_wo32(dev, gpuobj, pte++, offset_l | 3);
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else {
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nv_wo32(dev, gpuobj, pte++, offset_l | 0x21);
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nv_wo32(dev, gpuobj, pte++, offset_h & 0xff);
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}
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dma_offset += NV_CTXDMA_PAGE_SIZE;
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}
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}
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dev_priv->engine.instmem.finish_access(nvbe->dev);
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if (dev_priv->card_type == NV_50) {
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nv_wr32(dev, 0x100c80, 0x00050001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00000001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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}
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nvbe->bound = true;
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return 0;
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}
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static int
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nouveau_sgdma_unbind(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_device *dev = nvbe->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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unsigned i, j, pte;
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NV_DEBUG(dev, "\n");
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if (!nvbe->bound)
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return 0;
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dev_priv->engine.instmem.prepare_access(nvbe->dev, true);
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pte = nvbe->pte_start;
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for (i = 0; i < nvbe->nr_pages; i++) {
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dma_addr_t dma_offset = dev_priv->gart_info.sg_dummy_bus;
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for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++) {
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if (dev_priv->card_type < NV_50)
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nv_wo32(dev, gpuobj, pte++, dma_offset | 3);
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else {
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nv_wo32(dev, gpuobj, pte++, dma_offset | 0x21);
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nv_wo32(dev, gpuobj, pte++, 0x00000000);
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}
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dma_offset += NV_CTXDMA_PAGE_SIZE;
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}
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}
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dev_priv->engine.instmem.finish_access(nvbe->dev);
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if (dev_priv->card_type == NV_50) {
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nv_wr32(dev, 0x100c80, 0x00050001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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nv_wr32(dev, 0x100c80, 0x00000001);
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if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
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NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
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NV_ERROR(dev, "0x100c80 = 0x%08x\n",
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nv_rd32(dev, 0x100c80));
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return -EBUSY;
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}
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}
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nvbe->bound = false;
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return 0;
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}
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static void
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nouveau_sgdma_destroy(struct ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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if (be) {
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NV_DEBUG(nvbe->dev, "\n");
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if (nvbe) {
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if (nvbe->pages)
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be->func->clear(be);
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kfree(nvbe);
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}
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}
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}
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static struct ttm_backend_func nouveau_sgdma_backend = {
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nouveau_sgdma_bind,
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.unbind = nouveau_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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struct ttm_backend *
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nouveau_sgdma_init_ttm(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_sgdma_be *nvbe;
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if (!dev_priv->gart_info.sg_ctxdma)
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return NULL;
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nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL);
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if (!nvbe)
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return NULL;
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nvbe->dev = dev;
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nvbe->backend.func = &nouveau_sgdma_backend;
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return &nvbe->backend;
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}
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int
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nouveau_sgdma_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = NULL;
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uint32_t aper_size, obj_size;
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int i, ret;
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if (dev_priv->card_type < NV_50) {
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aper_size = (64 * 1024 * 1024);
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obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 4;
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obj_size += 8; /* ctxdma header */
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} else {
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/* 1 entire VM page table */
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aper_size = (512 * 1024 * 1024);
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obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 8;
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}
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ret = nouveau_gpuobj_new(dev, NULL, obj_size, 16,
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NVOBJ_FLAG_ALLOW_NO_REFS |
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &gpuobj);
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if (ret) {
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NV_ERROR(dev, "Error creating sgdma object: %d\n", ret);
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return ret;
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}
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dev_priv->gart_info.sg_dummy_page =
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alloc_page(GFP_KERNEL|__GFP_DMA32);
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set_bit(PG_locked, &dev_priv->gart_info.sg_dummy_page->flags);
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dev_priv->gart_info.sg_dummy_bus =
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pci_map_page(dev->pdev, dev_priv->gart_info.sg_dummy_page, 0,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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dev_priv->engine.instmem.prepare_access(dev, true);
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if (dev_priv->card_type < NV_50) {
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/* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and
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* confirmed to work on c51. Perhaps means NV_DMA_TARGET_PCIE
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* on those cards? */
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nv_wo32(dev, gpuobj, 0, NV_CLASS_DMA_IN_MEMORY |
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(1 << 12) /* PT present */ |
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(0 << 13) /* PT *not* linear */ |
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(NV_DMA_ACCESS_RW << 14) |
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(NV_DMA_TARGET_PCI << 16));
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nv_wo32(dev, gpuobj, 1, aper_size - 1);
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for (i = 2; i < 2 + (aper_size >> 12); i++) {
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nv_wo32(dev, gpuobj, i,
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dev_priv->gart_info.sg_dummy_bus | 3);
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}
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} else {
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for (i = 0; i < obj_size; i += 8) {
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nv_wo32(dev, gpuobj, (i+0)/4,
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dev_priv->gart_info.sg_dummy_bus | 0x21);
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nv_wo32(dev, gpuobj, (i+4)/4, 0);
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}
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}
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dev_priv->engine.instmem.finish_access(dev);
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dev_priv->gart_info.type = NOUVEAU_GART_SGDMA;
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dev_priv->gart_info.aper_base = 0;
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dev_priv->gart_info.aper_size = aper_size;
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dev_priv->gart_info.sg_ctxdma = gpuobj;
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return 0;
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}
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void
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nouveau_sgdma_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->gart_info.sg_dummy_page) {
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pci_unmap_page(dev->pdev, dev_priv->gart_info.sg_dummy_bus,
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NV_CTXDMA_PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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unlock_page(dev_priv->gart_info.sg_dummy_page);
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__free_page(dev_priv->gart_info.sg_dummy_page);
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dev_priv->gart_info.sg_dummy_page = NULL;
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dev_priv->gart_info.sg_dummy_bus = 0;
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}
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nouveau_gpuobj_del(dev, &dev_priv->gart_info.sg_ctxdma);
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}
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int
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nouveau_sgdma_get_page(struct drm_device *dev, uint32_t offset, uint32_t *page)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;
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int pte;
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pte = (offset >> NV_CTXDMA_PAGE_SHIFT);
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if (dev_priv->card_type < NV_50) {
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instmem->prepare_access(dev, false);
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*page = nv_ro32(dev, gpuobj, (pte + 2)) & ~NV_CTXDMA_PAGE_MASK;
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instmem->finish_access(dev);
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return 0;
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}
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NV_ERROR(dev, "Unimplemented on NV50\n");
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return -EINVAL;
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}
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