249 lines
7.0 KiB
C
249 lines
7.0 KiB
C
/*
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* OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
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*
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* Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
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* Copyright (C) 2008-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The PRM hardware modules on the OMAP2/3 are quite similar to each
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* other. The PRM on OMAP4 has a new register layout, and is handled
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* in a separate file.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
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#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
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#include "prcm-common.h"
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#include "prm.h"
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/*
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* Module specific PRM register offsets from PRM_BASE + domain offset
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*
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* Use prm_{read,write}_mod_reg() with these registers.
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*
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* With a few exceptions, these are the register names beginning with
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* {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
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* IRQSTATUS and IRQENABLE bits.)
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*/
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/* Register offsets appearing on both OMAP2 and OMAP3 */
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#define OMAP2_RM_RSTCTRL 0x0050
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#define OMAP2_RM_RSTTIME 0x0054
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#define OMAP2_RM_RSTST 0x0058
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#define OMAP2_PM_PWSTCTRL 0x00e0
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#define OMAP2_PM_PWSTST 0x00e4
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#define PM_WKEN 0x00a0
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#define PM_WKEN1 PM_WKEN
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#define PM_WKST 0x00b0
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#define PM_WKST1 PM_WKST
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#define PM_WKDEP 0x00c8
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#define PM_EVGENCTRL 0x00d4
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#define PM_EVGENONTIM 0x00d8
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#define PM_EVGENOFFTIM 0x00dc
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#ifndef __ASSEMBLER__
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#include <linux/io.h>
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#include "powerdomain.h"
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/* Power/reset management domain register get/set */
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static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
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{
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return readl_relaxed(prm_base + module + idx);
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}
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static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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writel_relaxed(val, prm_base + module + idx);
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}
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/* Read-modify-write a register in a PRM module. Caller must lock */
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static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
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s16 idx)
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{
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u32 v;
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v = omap2_prm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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omap2_prm_write_mod_reg(v, module, idx);
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return v;
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}
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/* Read a PRM register, AND it, and shift the result down to bit 0 */
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static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
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{
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u32 v;
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v = omap2_prm_read_mod_reg(domain, idx);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
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}
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static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
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{
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return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
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}
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/* These omap2_ PRM functions apply to both OMAP2 and 3 */
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int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
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int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod,
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u16 offset);
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int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part,
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s16 prm_mod, u16 reset_offset,
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u16 st_offset);
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extern int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
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extern int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
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extern int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm);
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extern int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst);
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extern int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst);
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extern int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
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extern int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
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extern int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
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extern int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm);
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extern int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2);
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extern int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2);
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extern int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2);
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extern int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm);
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#endif /* __ASSEMBLER */
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/*
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* Bits common to specific registers
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*
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* The 3430 register and bit names are generally used,
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* since they tend to make more sense
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*/
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/* PM_EVGENONTIM_MPU */
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/* Named PM_EVEGENONTIM_MPU on the 24XX */
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#define OMAP_ONTIMEVAL_SHIFT 0
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#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0)
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/* PM_EVGENOFFTIM_MPU */
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/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
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#define OMAP_OFFTIMEVAL_SHIFT 0
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#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0)
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/* PRM_CLKSETUP and PRCM_VOLTSETUP */
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/* Named PRCM_CLKSSETUP on the 24XX */
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#define OMAP_SETUP_TIME_SHIFT 0
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#define OMAP_SETUP_TIME_MASK (0xffff << 0)
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/* PRM_CLKSRC_CTRL */
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/* Named PRCM_CLKSRC_CTRL on the 24XX */
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#define OMAP_SYSCLKDIV_SHIFT 6
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#define OMAP_SYSCLKDIV_MASK (0x3 << 6)
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#define OMAP_SYSCLKDIV_WIDTH 2
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#define OMAP_AUTOEXTCLKMODE_SHIFT 3
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#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3)
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#define OMAP_SYSCLKSEL_SHIFT 0
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#define OMAP_SYSCLKSEL_MASK (0x3 << 0)
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/* PM_EVGENCTRL_MPU */
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#define OMAP_OFFLOADMODE_SHIFT 3
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#define OMAP_OFFLOADMODE_MASK (0x3 << 3)
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#define OMAP_ONLOADMODE_SHIFT 1
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#define OMAP_ONLOADMODE_MASK (0x3 << 1)
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#define OMAP_ENABLE_MASK (1 << 0)
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/* PRM_RSTTIME */
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/* Named RM_RSTTIME_WKUP on the 24xx */
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#define OMAP_RSTTIME2_SHIFT 8
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#define OMAP_RSTTIME2_MASK (0x1f << 8)
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#define OMAP_RSTTIME1_SHIFT 0
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#define OMAP_RSTTIME1_MASK (0xff << 0)
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/* PRM_RSTCTRL */
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/* Named RM_RSTCTRL_WKUP on the 24xx */
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/* 2420 calls RST_DPLL3 'RST_DPLL' */
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#define OMAP_RST_DPLL3_MASK (1 << 2)
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#define OMAP_RST_GS_MASK (1 << 1)
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/*
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* Bits common to module-shared registers
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*
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* Not all registers of a particular type support all of these bits -
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* check TRM if you are unsure
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*/
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/*
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* 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
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* called 'COREWKUP_RST'
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*
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* 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
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* RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
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*/
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#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3)
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/*
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* 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
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*
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* 2430: RM_RSTST_MDM
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*
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* 3430: RM_RSTST_CORE, RM_RSTST_EMU
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*/
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#define OMAP_DOMAINWKUP_RST_MASK (1 << 2)
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/*
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* 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
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* On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
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*
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* 2430: RM_RSTST_MDM
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*
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* 3430: RM_RSTST_CORE, RM_RSTST_EMU
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*/
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#define OMAP_GLOBALWARM_RST_SHIFT 1
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#define OMAP_GLOBALWARM_RST_MASK (1 << 1)
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#define OMAP_GLOBALCOLD_RST_SHIFT 0
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#define OMAP_GLOBALCOLD_RST_MASK (1 << 0)
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/*
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* 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
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* 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
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*
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* 2430: PM_WKDEP_MDM
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*
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* 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
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* PM_WKDEP_PER
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*/
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#define OMAP_EN_WKUP_SHIFT 4
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#define OMAP_EN_WKUP_MASK (1 << 4)
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/*
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* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
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* PM_PWSTCTRL_DSP
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*
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* 2430: PM_PWSTCTRL_MDM
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*
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* 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
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* PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
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* PM_PWSTCTRL_NEON
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*/
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#define OMAP_LOGICRETSTATE_MASK (1 << 2)
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#endif
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