196 lines
4.5 KiB
C
196 lines
4.5 KiB
C
/* linux/arch/arm/plat-s3c24xx/s3c244x.c
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*
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* Copyright (c) 2004-2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C2440 and S3C2442 Mobile CPU support (not S3C2443)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/sysdev.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <plat/cpu-freq.h>
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#include <mach/regs-clock.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-gpioj.h>
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#include <mach/regs-dsc.h>
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#include <plat/s3c2410.h>
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#include <plat/s3c2440.h>
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#include "s3c244x.h"
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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#include <plat/pll.h>
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static struct map_desc s3c244x_iodesc[] __initdata = {
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IODESC_ENT(CLKPWR),
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IODESC_ENT(TIMER),
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IODESC_ENT(WATCHDOG),
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};
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/* uart initialisation */
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void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
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}
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void __init s3c244x_map_io(void)
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{
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/* register our io-tables */
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iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
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/* rename any peripherals used differing from the s3c2410 */
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s3c_device_sdi.name = "s3c2440-sdi";
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s3c_device_i2c0.name = "s3c2440-i2c";
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s3c_device_nand.name = "s3c2440-nand";
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s3c_device_usbgadget.name = "s3c2440-usbgadget";
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}
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void __init_or_cpufreq s3c244x_setup_clocks(void)
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{
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struct clk *xtal_clk;
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unsigned long clkdiv;
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unsigned long camdiv;
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unsigned long xtal;
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unsigned long hclk, fclk, pclk;
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int hdiv = 1;
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xtal_clk = clk_get(NULL, "xtal");
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xtal = clk_get_rate(xtal_clk);
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clk_put(xtal_clk);
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fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
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clkdiv = __raw_readl(S3C2410_CLKDIVN);
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camdiv = __raw_readl(S3C2440_CAMDIVN);
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/* work out clock scalings */
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switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
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case S3C2440_CLKDIVN_HDIVN_1:
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hdiv = 1;
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break;
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case S3C2440_CLKDIVN_HDIVN_2:
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hdiv = 2;
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break;
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case S3C2440_CLKDIVN_HDIVN_4_8:
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hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
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break;
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case S3C2440_CLKDIVN_HDIVN_3_6:
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hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
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break;
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}
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hclk = fclk / hdiv;
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pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
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/* print brief summary of clocks, etc */
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printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
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print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
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s3c24xx_setup_clocks(fclk, hclk, pclk);
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}
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void __init s3c244x_init_clocks(int xtal)
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{
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/* initialise the clocks here, to allow other things like the
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* console to use them, and to add new ones after the initialisation
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*/
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s3c24xx_register_baseclocks(xtal);
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s3c244x_setup_clocks();
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s3c2410_baseclk_add();
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}
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#ifdef CONFIG_PM
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static struct sleep_save s3c244x_sleep[] = {
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SAVE_ITEM(S3C2440_DSC0),
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SAVE_ITEM(S3C2440_DSC1),
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SAVE_ITEM(S3C2440_GPJDAT),
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SAVE_ITEM(S3C2440_GPJCON),
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SAVE_ITEM(S3C2440_GPJUP)
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};
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static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
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{
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s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
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return 0;
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}
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static int s3c244x_resume(struct sys_device *dev)
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{
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s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
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return 0;
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}
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#else
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#define s3c244x_suspend NULL
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#define s3c244x_resume NULL
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#endif
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/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
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struct sysdev_class s3c2440_sysclass = {
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.name = "s3c2440-core",
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.suspend = s3c244x_suspend,
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.resume = s3c244x_resume
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};
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struct sysdev_class s3c2442_sysclass = {
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.name = "s3c2442-core",
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.suspend = s3c244x_suspend,
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.resume = s3c244x_resume
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};
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/* need to register class before we actually register the device, and
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* we also need to ensure that it has been initialised before any of the
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* drivers even try to use it (even if not on an s3c2440 based system)
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* as a driver which may support both 2410 and 2440 may try and use it.
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*/
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static int __init s3c2440_core_init(void)
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{
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return sysdev_class_register(&s3c2440_sysclass);
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}
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core_initcall(s3c2440_core_init);
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static int __init s3c2442_core_init(void)
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{
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return sysdev_class_register(&s3c2442_sysclass);
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}
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core_initcall(s3c2442_core_init);
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