Jisheng Zhang 44991eb4bf ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles ... For all BG2Q SoCs, 2 cycles is the best/correct value. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>		2014-06-16 13:09:04 +02:00
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compressed	Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into next	2014-06-05 15:57:04 -07:00
dts	ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles	2014-06-16 13:09:04 +02:00
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